📄 cntl_ddr2.vhd
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-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- -- OPB interface
-- OPB_ABus -- OPB address bus
-- OPB_DBus -- OPB data bus
-- Sln_DBus -- Slave read bus
-- OPB_select -- OPB Select
-- OPB_RNW -- OPB read not write
-- OPB_seqAddr -- OPB sequential address
-- OPB_BE -- OPB byte enables
-- Sln_xferAck -- Slave transfer acknowledge
-- Sln_errAck -- Slave Error acknowledge
-- Sln_toutSup -- Slave Timeout Suppress
-- Sln_retry -- Slave retry
--
-- -- DDR interface
-- DDR_Clk -- DDR clock(s)
-- DDR_Clkn -- DDR clock(s) negated
-- DDR_CKE -- DDR clock enable(s)
-- DDR_CSn -- DDR chip select(s)
-- DDR_RASn -- DDR row address strobe
-- DDR_CASn -- DDR column address strobe
-- DDR_WEn -- DDR write enable
-- DDR_DM -- DDR data mask
-- DDR_BankAddr -- DDR bank address
-- DDR_Addr -- DDR address
-- DDR_DQ_o -- DDR DQ output
-- DDR_DQ_i -- DDR DQ input
-- DDR_DQ_t -- DDR DQ output enable
-- DDR_DQS_i -- DDR DQS input
-- DDR_DQS_o -- DDR DQS output
-- DDR_DQS_t -- DDR DQS output enable
--
-- -- Clocks and reset
-- OPB_Clk -- OPB clock
-- OPB_Clk_n -- OPB clock shifted by 180
-- Clk90_in -- OPB clock shifted 90
-- Clk90_in_n -- OPB clock shifted by 270
-- DDR_Clk90_in -- DDR clock feedback shifted 90
-- DDR_Clk90_in_n -- DDR clock feedback shifted by 270
-- OPB_Rst -- OPB Reset
-------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity cntl_ddr2 is
generic (
-- ddr generics
C_INCLUDE_BURST_SUPPORT : integer := 1;
C_REG_DIMM : integer := 0;
C_NUM_BANKS_MEM : integer := 1;
-- supported number of memory banks, allowable values: 1-4. default = 1
C_NUM_CLK_PAIRS : integer := 1;
-- supported number of ddr clock pairs, allowable values: 1-4. default = 1
C_FAMILY : string := "spartan3";
-- ddr device generics
C_DDR_TMRD : integer := 15000;
C_DDR_TWR : integer := 15000;
C_DDR_TWTR : integer := 1;
C_DDR_TRAS : integer := 40000;
C_DDR_TRC : integer := 65000;
C_DDR_TRFC : integer := 75000;
C_DDR_TRCD : integer := 20000;
C_DDR_TRRD : integer := 15000;
C_DDR_TREFC : integer := 70000000;
C_DDR_TREFI : integer := 7800000;
C_DDR_TRP : integer := 20000;
C_DDR_CAS_LAT : integer := 2;
C_DDR_DWIDTH : integer := 16;
C_DDR_AWIDTH : integer := 13;
C_DDR_COL_AWIDTH : integer := 9;
C_DDR_BANK_AWIDTH : integer := 2;
-- address space generics
C_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_MEM3_HIGHADDR : std_logic_vector := x"00000000";
-- ipif generics
C_OPB_DWIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_CLK_PERIOD_PS : integer := 10000;
-- simulation only generic
C_SIM_INIT_TIME_PS : integer := 200000000
);
port
(
-- Test Bus
ddr_test_cntl : in std_logic_vector(1 downto 0);
ddr_test_bus : out std_logic_vector(19 downto 0);
-- OPB Port Declarations ***********************************************
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1 );
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1 );
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1 );
OPB_select : in std_logic := '0';
OPB_RNW : in std_logic := '0';
OPB_seqAddr : in std_logic := '0';
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
-- DDR interface signals
DDR_Clk : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1);
DDR_Clkn : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1);
DDR_CKE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
DDR_CSn : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
DDR_RASn : out std_logic;
DDR_CASn : out std_logic;
DDR_WEn : out std_logic;
DDR_DM : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_BankAddr : out std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
DDR_Addr : out std_logic_vector(0 to C_DDR_AWIDTH-1);
DDR_DQ_o : out std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DQ_i : in std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DQ_t : out std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DQS_i : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_DQS_o : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_DQS_t : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_Init_done : out std_logic;
-- Clocks and reset
OPB_Clk : in std_logic;
OPB_Clk_n : in std_logic;
Clk90_in : in std_logic;
Clk90_in_n : in std_logic;
DDR_Clk90_in : in std_logic;
DDR_Clk90_in_n : in std_logic;
OPB_Rst : in std_logic
);
-- fan-out attributes for Synplicity
attribute SYN_MAXFAN : integer;
attribute SYN_MAXFAN of OPB_Clk : signal is 10000;
attribute SYN_MAXFAN of OPB_Rst : signal is 10000;
--fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of OPB_Clk : signal is "1000";
attribute MAX_FANOUT of OPB_Rst : signal is "1000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
attribute RUN_NGCBUILD : string;
attribute RUN_NGCBUILD of cntl_ddr2 : entity is "TRUE";
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_MEM0_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_MEM1_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_MEM2_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_MEM3_BASEADDR : constant is "0x08";
attribute ASSIGNMENT : string;
attribute ASSIGNMENT of C_MEM0_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_MEM0_HIGHADDR : constant is "REQUIRE";
attribute XRANGE : string;
attribute XRANGE of C_NUM_BANKS_MEM : constant is "(1:4)";
attribute XRANGE of C_NUM_CLK_PAIRS : constant is "(1:4)";
attribute XRANGE of C_DDR_CAS_LAT : constant is "(2,3)";
attribute XRANGE of C_DDR_DWIDTH : constant is "(16)";
attribute ADDR_TYPE : string;
attribute ADDR_TYPE of C_MEM0_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM0_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM1_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM1_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM2_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM2_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM3_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_MEM3_HIGHADDR : constant is "MEMORY";
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end cntl_ddr2;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cntl_ddr2 is
component ddr_controller2 is
generic (
C_FAMILY : string := "virtex2";
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_NUM_CLK_PAIRS : integer range 1 to 4 := 1;
C_REG_DIMM : integer := 0;
C_DDR_TMRD : integer := 15000;
C_DDR_TWR : integer := 15000;
C_DDR_TWTR : integer := 1;
C_DDR_TRAS : integer := 40000;
C_DDR_TRC : integer := 65000;
C_DDR_TRFC : integer := 75000;
C_DDR_TRCD : integer := 20000;
C_DDR_TRRD : integer := 15000;
C_DDR_TREFC : integer := 70000000;
C_DDR_TREFI : integer := 7800000;
C_DDR_TRP : integer := 20000;
C_DDR_CAS_LAT : integer := 2;
C_DDR_DWIDTH : integer := 32;
C_DDR_AWIDTH : integer := 13;
C_DDR_COL_AWIDTH : integer := 9;
C_DDR_BANK_AWIDTH : integer := 2;
C_DDR_BRST_SIZE : integer := 8;
C_IPIF_DWIDTH : integer := 64;
C_IPIF_AWIDTH : integer := 32;
C_INCLUDE_BURSTS : integer := 1;
C_CLK_PERIOD : integer := 10000;
C_OPB_BUS : integer := 0;
C_PLB_BUS : integer := 1;
-- simulation only generic (set to 200us)
C_SIM_INIT_TIME_PS : integer := 200000000;
C_INCLUDE_ECC_SUPPORT : integer := 0;
NUM_ECC_BITS : integer := 7
);
port (
-- Test Bus
ddr_test_cntl : in std_logic_vector(1 downto 0);
ddr_test_bus : out std_logic_vector(19 downto 0);
-- IPIC inputs
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_RNW : in std_logic;
Bus2IP_RdReq : in std_logic;
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