📄 cntl_ddr2.vhd
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-------------------------------------------------------------------------------
-- $Id: opb_ddr.vhd,v 1.2 2005/01/17 21:47:56 sid Exp $
-------------------------------------------------------------------------------
-- opb_ddr.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ddr.vhd
-- Version: v1.10a
-- Description: Top level file for OPB DDR controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- cntl_ddr.vhd
-- -- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
-- -- opb_ipif.vhd
--
-------------------------------------------------------------------------------
-- Change log:
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
-- ***************************************************************************
-- New version: cntl_ddr_v1_10_b
--
-- Parameter modications:
-- => Supports multiple memory banks (up to 4) with C_NUM_BANKS_MEM generic.
-- => C_BASEADDR generic is now C_MEM0_BASEADDR.
-- => C_HIGHADDR generic is now C_MEM0_HIGHADDR.
-- => Supports multiple DDR clock paris (up to 4) with C_NUM_CLK_PAIRS generic.
-- => C_DQS_PULLUPS parameter is removed. The new default setting assumes pullups.
--
-- Port modifications:
-- => Requires additional clock inputs: plb_clk_n, clk90_in_n, and ddr_clk90_in_n
-- => DDR_Clk is now a vectorized signal, DDR_Clk = DDR_Clk(0)
-- => DDR_Clkn is now a vectorized signal, DDR_Clkn = DDR_Clkn(0)
-- => DDR_CKE is now a vectorized signal, DDR_CKE = DDR_CKE(0)
-- => DDR_CSn is now a vectorized signal, DDR_CSn = DDR_CSn(0)
--
-- ***************************************************************************
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gmm_SP1
-- ***************************************************************************
--
-- Modified DDR_DQS IOB input register instantiation for Virtex-4 systems.
-- DDR_DQS register is no longer registered in IOB, due to reset/set signal
-- differences in the Virtex-4 ILOGIC cell model. Please note that UCF
-- timing constraints are necessary with this modification. Please refer
-- to Xilinx Solution Record # 20202 found on http://www.support.xilinx.com/
-- for more information.
--
-- ***************************************************************************
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: DAB
-- History:
-- ALS 05/28/02 First Version
-- ^^^^^^
-- First version of OPB DDR controller
-- ~~~~~~
-- ALS 06/11/02
-- ^^^^^^
-- Added Clk, Clk90, and Clk_DDR_Rddata outputs.
-- ~~~~~~
-- ALS 07/23/02
-- ^^^^^^
-- Updated to version B, includes new generics and hooks to include burst
-- support when IPIF supports it.
-- ~~~~~~
-- ALS 09/10/02
-- ^^^^^^
-- Allow C_REG_DIMM generic to be user modifiable.
-- ~~~~~~
-- ALS 10/03/02
-- ^^^^^^
-- Removed all generics associated with the DCMs. Added generic to indicate
-- if the DDR DQS lines were pulled up or down. Renamed DDR_Clk_in to
-- DDR_Clk90_in. Removed the following ports:
-- Clk
-- Clk90
-- Clk_DDR_RdData
-- Clk90_locked
-- Clkddr_locked
-- DCM_Rst
-- ~~~~~~
-- ALS 01/23/04 Version 1.00c
-- ^^^^^^
-- Implemented latest OPB IPIF to support bursting. Removed DUMMY entries
-- in areas.
-- ~~~~~~
-- JLJ 04/19/04 Version 1.10a
-- ^^^^^^
-- Updated to version 1.10a and includes DDR core version v1.10a. New version
-- includes:
--
-- => Support for multiple memory banks (up to 4) with C_NUM_BANKS_MEM generic.
--
-- => Modified DDR_CKE to size with the number of memory banks (C_NUM_BANKS_MEM generic).
-- Renamed DDR_CKE to DDR_CKE(0:C_NUM_BANKS_MEM-1).
--
-- => Support new input clock requirements. Add PLB_Clk_n, Clk90_in_n,
-- and DDR_Clk90_in_n signals on port mapping for DDR core. This update
-- of the core requires global inversion on clock inputs to prevent any
-- duty cycle distortion as system frequencies increase.
--
-- => Create multiple DDR clock pairs to support clocking requirements
-- of certain DDR SDRAM DIMM vendors. Added support for up to 3 differential
-- DDR clock pairs.
-- Added new parameter, C_NUM_CLK_PAIRS with allowable values 1-4.
-- Renamed DDR_Clk and DDR_Clkn to DDR_Clk(0:C_NUM_CLK_PAIRS-1) and
-- DDR_Clkn(0:C_NUM_CLK_PAIRS-1).
--
-- => Removed C_DQS_PULLUPS generic. If this parameter was set to 1, the DDR
-- DQS lines had pullups. If this parameter was set to 0, then pulldowns
-- were assumed. The new default setting will assume pullups.
--
-- => Update to proc_common_v2_00_a. Removed ipif_common_v1_00_d.
--
-- => Update to opb_ipif_v3_01_a which supports bursting.
--
-- => Added support for Virtex4.
--
-- => Add latest PSFUtil MPD attributes to top level entity.
--
-- ~~~~~~
-- JLJ 10/20/04 Version 1.10a
-- ^^^^^^
-- Remove IOB TRUE attribute on DDR_DQS signal for Virtex-4 in ddr_v1_10_a support
-- library in io_registers.vhd.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
use proc_common_v2_00_a.family.all;
use proc_common_v2_00_a.all;
library ddr_v1_10_a;
--use ddr_v1_10_a.ddr_controller;
library opb_ipif_v3_01_b;
use opb_ipif_v3_01_b.opb_ipif;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- OPB DDR Generics
-- C_INCLUDE_BURST_SUPPORT -- support bus burst transactions
-- C_REG_DIMM -- include pipeline stage to support Reg DIMM
-- C_NUM_BANKS_MEM -- supported number of memory banks
-- C_NUM_CLK_PAIRS -- supported number of DDR clock pairs
-- C_FAMILY -- target FPGA family
--
-- -- DDR SDRAM Device Generics
-- C_DDR_TMRD -- Load Mode Register command cycle time
-- C_DDR_TWR -- write recovery time
-- C_DDR_TWTR -- write-to-read recovery time
-- C_DDR_TRAS -- delay after ACTIVE command before
-- -- PRECHARGE command
-- C_DDR_TRC -- delay after ACTIVE command before
-- -- another ACTIVE or AUTOREFRESH command
-- C_DDR_TRFC -- delay after AUTOREFRESH before another command
-- C_DDR_TRCD -- delay after ACTIVE before READ/WRITE
-- C_DDR_TRRD -- delay after ACTIVE row a before ACTIVE
-- -- row b
-- C_DDR_TRP -- delay after PRECHARGE command
-- C_DDR_TREFC -- refresh to refresh command interval
-- C_DDR_TREFI -- average periodic refresh command interval
-- C_DDR_CAS_LAT -- CAS latency
-- C_DDR_DWIDTH -- DDR data width of each device
-- C_DDR_AWIDTH -- DDR row address width
-- C_DDR_COL_AWIDTH -- DDR column address width
-- C_DDR_BANK_AWIDTH -- DDR bank address width
--
-- -- Address Space Generics
-- C_MEM0_BASEADDR -- DDR memory bank 0 base address
-- C_MEM0_HIGHADDR -- DDR memory bank 0 high address
-- C_MEM1_BASEADDR -- DDR memory bank 1 base address
-- C_MEM1_HIGHADDR -- DDR memory bank 1 high address
-- C_MEM2_BASEADDR -- DDR memory bank 2 base address
-- C_MEM2_HIGHADDR -- DDR memory bank 2 high address
-- C_MEM3_BASEADDR -- DDR memory bank 3 base address
-- C_MEM3_HIGHADDR -- DDR memory bank 3 high address
--
-- -- OPB Bus Interface Generics
-- C_OPB_DWIDTH -- OPB data width
-- C_OPB_AWIDTH -- OPB address width
-- C_OPB_CLK_PERIOD_PS -- clock period in pico-seconds
--
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