📄 command_statemachine.vhd
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-------------------------------------------------------------------------------
-- $Id: command_statemachine.vhd,v 1.3 2004/06/01 19:59:03 jennj Exp $
-------------------------------------------------------------------------------
-- command_statemachine.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: command_statemachine.vhd
-- Version: v1.10a
-- Description: This state machine controls the application of commands
-- to the DDR.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/07/02 First Version
--
-- ALS 06/04/02
-- ^^^^^^
-- Simplified state machine by removing READ_DATA and WRITE_DATA states. Since
-- READ_CMD and WRITE_CMD states issue the commands, there is no need for the
-- READ_DATA and WRITE_DATA states.
-- ~~~~~~
-- ALS 06/06/02
-- ^^^^^^
-- In states that assert RETRY, must wait for Bus2IP_CS to negate before going
-- back to IDLE so that the bus has had time to react to the retry.
-- ~~~~~~
-- ALS 06/11/02
-- ^^^^^^
-- Generate DQ_OE_CMB during WRITE_CMD state. This will be used in the IOB register
-- to assert DQT. DQ_OE_CMB will be registered by falling edge register and then
-- used to reset the DQS IOB register and used in the IOB register to assert DQST.
-- DQS and DQST are clocked by CLK90, so the falling edge pipe register helps
-- the path delay.
-- ~~~~~~
-- ALS 06/20/02
-- ^^^^^^
-- Fixed WAIT_TRAS state - Write op and read op may be already negated. Created
-- signals write_state and read state instead.
-- ~~~~~~
-- ALS 07/16/02
-- ^^^^^^
-- Major cleanup - with this version of IPIF, can't have a pend_wrreq or pend_rdreq
-- during a read or write command, so take all of this extra code out. Also, need
-- to make changes to support IPIF bursts (PLB)
-- ~~~~~~
-- ALS 05/01/03
-- ^^^^^^
-- Problem with BUS2IP_CS still being asserted after data cycle finished. This
-- caused state machine to go to ACT_CMD state to activate the row. However,
-- this state didn't re-examine BUS2IP_CS until Trcd expired, so the case existed
-- where BUS2IP_CS could negate and re-assert for the next transaction while
-- in the ACT_CMD state causing the correct row to not be activated and data
-- to be accessed from the previous row.
-- Modified ACT_CMD state to examine BUS2IP_CS every clock.
-- ~~~~~~
-- ALS 06/25/03
-- ^^^^^^
-- Cleaned up code - added generation of addrAck
-- ALS 06/27/03
-- ^^^^^^
-- Made DQS_OE, DQS_RST, and DQS_SETRST vectors so that there is an individual
-- enable for each DQS line. This reduces the fan-out on this signal and makes
-- the CLK - CLK90 timing easier to meet. Instantiated primitives so that
-- the synthesis tools would not optimize the redundant registers away.
-- ~~~~~~
-- ALS 07/01/03
-- ^^^^^^
-- Command state machine now uses RdReq instead of Burst to correctly end the
-- read cycle. Precharge is now issued before all of the data is read as allowed
-- in the data sheet. Read_data_done is tested to be asserted before leaving PRECHARGE
-- ~~~~~~
-- ALS 07/15/03
-- ^^^^^^
-- Will assert TOUTSUP in all states except IDLE and PRECHARGE. The PRECHARGE
-- state waits for Read_data_done, therefore, will want the timeout counter
-- to be activated during this state to report an error if the state machine
-- stays in the PRECHARGE state. Also, modified code to generate "read_pause"
-- which signals the data state machine that the read transaction has been
-- interrupted to service a refresh or because a row or bank has rolled over.
-- ~~~~~~
-- JLJ 11/12/03
-- ^^^^^^
-- Version D: Add support/creation for the following signals:
-- DQ_ECC_oe_cmb
-- DQS_ECC_oe
-- DQS_ECC_rst
-- DQS_ECC_setrst
--
-- ~~~~~~
-- JLJ 02/13/04
-- ^^^^^^
-- Add Bus2IP_CS to reset condition of read_pause signal. Used to finish data
-- state machine when burst is finished while executing refresh.
-- ~~~~~~
-- JLJ 02/16/04
-- ^^^^^^
-- Add C_INCLUDE_BURSTS parameter for optimization enhancements.
-- ~~~~~~
-- JLJ 02/20/04
-- ^^^^^^
-- Support multiple CS with parameter C_NUM_BANKS_MEM. Modify port to bring in
-- Comb_Bus2IP_CS (combined Bus2IP_CS signal).
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-- JLJ 05/31/04
-- ^^^^^^
-- Modify assertion of Retry in PRECHARGE state to PLB bus only.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DDR_AWIDTH -- DDR address width
-- C_DDR_COL_AWIDTH -- DDR column address width
-- C_DDR_BANK_AWIDTH -- DDR bank address width
-- C_MRDCNT -- Tmrd clock cycles
-- C_RFCCNT -- Trfc clock cycles
-- C_RCDCNT -- Trcd clock cycles
-- C_RPCNT -- Trp clock cycles
-- C_GP_CNTR_WIDTH -- Width of general purpose counter
-- C_OPB_BUS -- Processor bus is OPB
-- C_PLB_BUS -- Processor bus is PLB
-- C_INCLUDE_BURSTS -- Include support for bus burst transactions
-- NUM_ECC_BITS -- Number of ECC bits
--
-- Definition of Ports:
-- -- IPIC interface
-- -- inputs
-- Comb_Bus2IP_CS -- indicates DDR SDRAM controller has been selected
-- Bus2IP_CS -- indicates active memory bank
-- Burst -- processor burst transaction
-- Row_addr -- row address
-- Col_addr -- column address
-- Bank_addr -- bank address
-- Bus2IP_RdReq -- read request
-- Bus2IP_WrReq -- write request
-- Pend_rdreq -- pending read request
-- Pend_wrreq -- pending write request
-- Same_row -- access is within the same row
-- Same_bank -- access is within the same bank
-- --outputs
-- Read_dqs_ce -- clock enable to read dqs
-- Retry -- retry signal
-- Rd_AddrAck -- read cycle address acknowledge
-- Wr_AddrAck -- write cycle address acknowledge
-- Reset_pendrdreq -- reset pending read request
-- Reset_pendwrreq -- reset pending write request
-- ToutSup -- suppress timeout counter
--
-- -- Init SM interface
-- --inputs
-- Refresh -- issue refresh command
-- Precharge -- issue precharge command
-- Load_mr -- issue load_mr command
-- Register_data -- data for the Mode or Extended Mode registers
-- Register_sel -- selects either the Mode or Extended Mode register
-- Init_done -- indicates initialization sequence is complete
-- -- outputs
-- CMD_idle -- output indicating command sm is in IDLE state
--
-- -- Data SM interface
-- -- inputs
-- Read_data_done -- done with read data reception
-- -- outputs
-- Read_data_done_rst -- reset Read_data_done
-- Pend_write -- start transmitting write data
-- Pend_read -- start receiving read data
-- Read_pause -- read transfer is interrupted
--
-- -- Counters interface
-- -- inputs
-- Trefi_end -- time to issue a refresh command
-- Trc_end -- end of active row to active row delay
-- Trrd_end -- end of active row to active row delay
-- Tras_end -- end of active to precharge delay
-- Twr_end -- end of write to precharge delay
-- GPcnt_end -- general purpose timer ended
-- Tcmd_end -- brst len/2 counter ended
--
-- -- outputs
-- Twr_rst -- reset Twr counter
-- Tcmd_load -- load Tcmd counter
-- Tcmd_cnt_en -- enable Tcmd counter
-- Trefi_load -- re-load refresh interval timer
-- Trc_load -- load active row to active row timer
-- Trrd_load -- load active row to active row timer
-- Tras_load -- load active to precharge timer
-- GPcnt_load -- load the general purpose timer
-- GPcnt_en -- enable the general purpose timer
-- GPcnt_data -- count to load into the general purpose timer
--
-- -- IOB Register Interface
-- DDR_CSn -- memory chip selects
-- DDR_RASn -- Row address strobe
-- DDR_CASn -- Column address strobe
-- DDR_WEn -- Write enable
-- DDR_Addr -- address
-- DDR_BankAddr -- bank address
-- DQ_oe_cmb -- combinational DQ output enable
-- DQS_oe -- registered DQS output enable
-- DQS_rst -- reset DQS
-- DQS_setrst -- DQS set/reset
-- DQ_ECC_oe_cmb -- combinational DQ ECC output enable
-- DQS_ECC_oe -- registered DQS ECC output enable
-- DQS_ECC_rst -- reset DQS ECC
-- DQS_ECC_setrst -- DQS ECC set/reset
--
-- -- Clocks and reset
-- Clk
-- Rst
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity command_statemachine is
generic (
C_DDR_AWIDTH : integer;
C_DDR_DWIDTH : integer;
C_DDR_COL_AWIDTH : integer;
C_DDR_BANK_AWIDTH : integer;
C_REG_DIMM : integer;
C_MRDCNT : std_logic_vector;
C_RFCCNT : std_logic_vector;
C_RCDCNT : std_logic_vector;
C_RPCNT : std_logic_vector;
C_GP_CNTR_WIDTH : integer;
C_OPB_BUS : integer := 0;
C_PLB_BUS : integer := 1;
C_INCLUDE_BURSTS : integer;
C_INCLUDE_ECC_SUPPORT : integer;
C_NUM_BANKS_MEM : integer range 1 to 4 := 1
);
port (
-- IPIC
Comb_Bus2IP_CS : in std_logic;
Bus2IP_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Row_addr : in std_logic_vector(0 to C_DDR_AWIDTH-1);
Col_addr : in std_logic_vector(0 to C_DDR_AWIDTH-1);
Bank_addr : in std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
Pend_rdreq : in std_logic;
Pend_wrreq : in std_logic;
Same_row : in std_logic;
Same_bank : in std_logic;
Read_dqs_ce : out std_logic;
Retry : out std_logic;
Rd_AddrAck : out std_logic;
Wr_AddrAck : out std_logic;
Reset_pendrdreq : out std_logic;
Reset_pendwrreq : out std_logic;
ToutSup : out std_logic;
-- Init SM interface
Refresh : in std_logic;
Precharge : in std_logic;
Load_mr : in std_logic;
Register_data : in std_logic_vector(0 to C_DDR_AWIDTH-1);
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