📄 data_statemachine.vhd
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-------------------------------------------------------------------------------
-- $Id: data_statemachine.vhd,v 1.1 2004/04/06 23:13:04 jennj Exp $
-------------------------------------------------------------------------------
-- data_statemachine.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: data_statemachine.vhd
-- Version: v1.10a
-- Description: This state machine controls the power-up sequence of commands
-- to the DDR.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/07/02 First Version
--
-- ALS 06/07/02
-- ^^^^^^
-- Made changes to support Asynch FIFO read data interface:
-- -- generate READ_DATA_EN sooner
-- -- remove RDACK generation
-- ~~~~~~
-- ALS 07/12/02
-- ^^^^^^
-- Added C_REG_DIMM generic. When C_REG_DIMM=1, add a 1-clock pipeline
-- delay to write_data, write_data_mask, write_data_en, write_dqs_en.
-- ~~~~~~
-- ALS 07/17/02
-- ^^^^^^
-- Drastically changed state machine to simplify it. No longer need to monitor
-- burst signal - will use pend_wr and pend_rd instead.
-- ~~~~~~
-- ALS 06/27/03
-- ^^^^^^
-- Made WRITE_DQS_EN a vector so that there is an individual enable for each
-- DQS line. This reduces the fan-out on this signal and makes the CLK - CLK90
-- timing easier to meet.
-- ~~~~~~
-- ALS 07/01/03
-- ^^^^^^
-- Use Bus2IP_Burst to control data phase instead of pend_read as command state
-- machine will leave read state earlier. Also, will register and hold data_done
-- as it signals when the command state machine can service the next command.
-- ~~~~~~
-- ALS 07/15/03
-- ^^^^^^
-- Since DQS pullups will look like DQS is asserted, have to determine
-- when to reset the read acknowledge. This requires knowing when the read
-- transaction has been interrupted to service a refresh or because the row
-- or bank has changed. Implemented a counter to count clocks in which the
-- read command has been issued so that the read acknowledge can be reset
-- when the proper number of read acknowledges have been received. This is
-- only needed when a read transaction has been interrupted.
-- ~~~~~~
-- JLJ 11/11/03
-- ^^^^^^
-- Version D: Include support for ECC. Add write ECC data registers.
-- ~~~~~~
-- JLJ 02/13/04
-- ^^^^^^
-- Add Bus2IP_CS into RD_DATA state logic for handling condition when
-- burst finishes while executing a refresh.
-- ~~~~~~
-- JLJ 02/16/04
-- ^^^^^^
-- Add C_INCLUDE_BURSTS parameter for optimization enhancements.
-- ~~~~~~
-- JLJ 02/20/04
-- ^^^^^^
-- Support multiple CS with parameter C_NUM_BANKS_MEM. Modify port to bring in
-- Comb_Bus2IP_CS (combined Bus2IP_CS signal) to replace Bus2IP_CS.
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DDR_DWIDTH -- width of DDR address bus
-- C_IPIF_DWIDTH -- width of processor bus
-- C_REG_DIMM -- add clock delay on write data, etc. for reg dimms
-- C_INCLUDE_BURSTS -- include support for bus burst transactions
-- NUM_ECC_BITS -- number of ECC check bits
--
-- Definition of Ports:
-- -- inputs
-- IPIC_wrdata -- data to be written
-- ECC_chk_bits_wr -- ECC data to be written
-- IPIC_be -- bus byte enables
-- Pend_write -- enable writing of data
-- Pend_read -- enable reading of data
-- DDR_brst_end -- end of ddr burst
-- Tcaslat_end -- CAS latency end
-- Twr_end -- Twr end
-- Rdack -- read data acknowledge
-- Read_data_done_rst -- reset read data done register
-- Read_pause -- pause in read transfer due to row/bank rollover or refresh
--
-- -- outputs
-- WrAck -- write acknowledge
-- Read_data_en -- enable read data io register
-- Write_data_en -- enable write data io register
-- Write_data_ecc_en -- enable write ecc data io register
-- Write_dqs_en -- enable write dqs io register
-- Write_dqs_ecc_en -- enable write ecc dqs io register
-- Write_data -- data to be written
-- Write_data_ecc -- ECC data to be written
-- Write_data_mask -- data mask to be written
-- Write_data_ecc_mask -- ECC data mask to be written
-- Read_data_done -- data statemachine is complete
-- Tbrst_cnt_en -- enable burst counter
-- Tbrst_load -- load burst counter
-- Tcaslat_cnt_en -- enable CAS latency counter
-- Tcaslat_load -- load CAS latency counter
-- Twr_load -- load Twr counter
-- Twr_cnten -- enable Twr counter
-- Rst_pend_rd -- reset pending read
-- Rst_pend_wr -- reset pending write
--
-- -- Clocks and reset
-- Clk
-- Rst
---------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity data_statemachine is
generic ( C_DDR_DWIDTH : integer;
C_IPIF_DWIDTH : integer;
C_REG_DIMM : integer;
C_INCLUDE_BURSTS : integer;
C_INCLUDE_ECC_SUPPORT : integer;
NUM_ECC_BITS : integer
);
port (
-- inputs
IPIC_wrdata : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_wr : in std_logic_vector(0 to NUM_ECC_BITS*2-1); -- ECC
IPIC_be : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Comb_Bus2IP_CS : in std_logic;
Pend_write : in std_logic;
Pend_read : in std_logic;
DDR_brst_end : in std_logic;
Tcaslat_end : in std_logic;
Twr_end : in std_logic;
Rdack : in std_logic;
Read_data_done_rst : in std_logic;
Read_pause : in std_logic;
-- outputs
WrAck : out std_logic;
Read_data_en : out std_logic;
Write_data_en : out std_logic;
Write_data_ecc_en : out std_logic; -- ECC
Write_dqs_en : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
Write_dqs_ecc_en : out std_logic; -- ECC
Write_data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
Write_data_ecc : out std_logic_vector(0 to NUM_ECC_BITS*2-1); -- ECC
Write_data_mask : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Write_data_ecc_mask : out std_logic_vector (0 to C_IPIF_DWIDTH/32-1); -- ECC
Read_data_done : out std_logic;
Tbrst_cnt_en : out std_logic;
Tbrst_load : out std_logic;
Tcaslat_cnt_en : out std_logic;
Tcaslat_load : out std_logic;
Twr_load : out std_logic;
Twr_cnten : out std_logic;
RdAck_rst : out std_logic;
-- Clocks and reset
Clk : in std_logic;
Rst : in std_logic
);
end entity data_statemachine;
-----------------------------------------------------------------------------
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