read_data_path2_old.vhd

xilinx ddr3最新VHDL代码,通过调试

        C_LD_OFFSET   : natural :=  0;
        C_AD_WIDTH    : natural :=  8;
        C_AD_OFFSET   : natural :=  0
    );
    port (
        CK       : in  std_logic;
        RST      : in  std_logic; 
        Q        : out std_logic_vector(0 to C_REG_WIDTH-1);
        LD       : in  std_logic_vector(0 to C_LD_WIDTH-1); 
        AD       : in  std_logic_vector(0 to C_AD_WIDTH-1); 
        LOAD     : in  std_logic;  
        OP       : in  std_logic   
       );
end component ld_arith_reg;
 
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin  

-------------------------------------------------------------------------------
-- Test Output
-------------------------------------------------------------------------------
test_bus_reg1: process(Clk)
begin
    if Clk'event and Clk = '1' then
      if ddr_test_cntl = "00" then
         ddr_rd_bus(19)  <=  fifo_rst;
         ddr_rd_bus(18)  <=  fifo_rden;
         ddr_rd_bus(5 downto 0)    <=  read_data_i(2 to 7);
      end if;
     end if;
end process;

-- test_bus_reg2: process(Clk_ddr_rddata)
-- begin
--     if Clk_ddr_rddata'event and Clk_ddr_rddata = '1' then
--       if ddr_test_cntl = "00" then
--          ddr_rd_bus(7 downto 6)    <=  fifo_wren(0 to 1);
--          ddr_rd_bus(17 downto 16)  <=  DDR_ReadDQS;
--          ddr_rd_bus(15 downto 12)  <=  DDR_ReadData(0 to 3);         
--          ddr_rd_bus(11 downto 8)   <=  DDR_ReadData(16 to 19);         
--        end if;
--      end if;
-- end process;

 test_bus_reg2: process(Clk)
 begin
     if Clk'event and Clk = '1' then
       --if ddr_test_cntl = "00" then
          ddr_rd_bus(7 downto 6)    <=  fifo_wren(0 to 1);
          -- ddr_rd_bus(7 downto 6)    <=  DDR_ReadDQS;
          ddr_rd_bus(17 downto 16)  <=  DDR_ReadDQS;
          ddr_rd_bus(15 downto 12)  <=  DDR_ReadData(0 to 3);         
          ddr_rd_bus(11 downto 8)   <=  DDR_ReadData(16 to 19);         
       -- end if;
      end if;
 end process;
 

  
-------------------------------------------------------------------------------
-- FIFO control signals
-------------------------------------------------------------------------------
-- write the FIFOs when the DDR asserts the data strobe
FIFO_WREN_GEN: for i in 0 to C_IPIF_DWIDTH/16-1 generate
begin
    FIFO_WREN_GATE_PROCESS: process(Clk_ddr_rddata)
    begin
        if Clk_ddr_rddata'event and Clk_ddr_rddata = '1' then
            if DDR_read_data_en = '0' then
                fifo_wren_gate(i) <= '0';
            elsif DDR_ReadDQS(i)='0' then
                fifo_wren_gate(i) <= '1';
            end if;
        end if;
    end process FIFO_WREN_GATE_PROCESS;
    
    fifo_wren(i)  <= '1' when (DDR_ReadDQS(i)='1' and fifo_wren_gate(i)='1')
                        else '0';
end generate FIFO_WREN_GEN;

-- read the FIFOs when all FIFOs are not empty
fifo_rden <= '1' when fifo_empty = ZERO_EMPTY
            else '0';
-- reset the FIFOs when the read data phase is over
FIFO_RST_REG: process(Clk)
begin
    if Clk'event and Clk = '1' then
        if Rst = RESET_ACTIVE then
            fifo_rst <= RESET_ACTIVE;
        else
            fifo_rst <= not(Read_data_en);
        end if;
     end if;
end process FIFO_RST_REG;
-------------------------------------------------------------------------------
-- Generate RdAck 
-------------------------------------------------------------------------------
RDACK_PROCESS: process(Clk)
begin
    if Clk'event and Clk='1' then
       if Rst = RESET_ACTIVE or RdAck_rst = '1' then
            rdack_i <= '0';
        else 
            rdack_i <= fifo_rden;
        end if;
    end if;
end process RDACK_PROCESS;
RdAck <= rdack_i;

-------------------------------------------------------------------------------
-- Instantiate the FIFOs
-------------------------------------------------------------------------------
-- use one FIFO for each DQS. Since there are two bytes from the DDR each clock,
-- one DQS bit corresponds to 16-bit data. Therefore, instantiate 16-bit wide
-- FIFOs
FIFO_GEN: for i in 0 to C_IPIF_DWIDTH/16-1 generate
    V2_ASYNCH_FIFO_I: async_fifo_v4_0
    generic map(
        c_enable_rlocs => 0,
        c_data_width => 16,
        c_fifo_depth => 15,
        c_has_almost_full => 0,
        c_has_almost_empty => 0,
        c_has_wr_count => 0,
        c_has_rd_count => 0,
        c_wr_count_width => 2,
        c_rd_count_width => 2,
        c_has_rd_ack => 0,
        c_rd_ack_low => 0,
        c_has_rd_err => 0,
        c_rd_err_low => 0,
        c_has_wr_ack => 0,
        c_wr_ack_low => 0,
        c_has_wr_err => 0,
        c_wr_err_low => 0,
        c_use_blockmem => 0
        )
    port map (
        din     => DDR_ReadData(i*16 to i*16+15),
        wr_en   => fifo_wren(i),
        wr_clk  => Clk_ddr_rddata,
        rd_en   => fifo_rden,
        rd_clk  => Clk,
        ainit   => fifo_rst,
        dout    => read_data_i(i*16 to i*16+15),
        full    => open,
        empty   => fifo_empty(i),
        almost_full  => open,
        almost_empty => open,
        wr_count     => open,
        rd_count     => open,
        rd_ack       => open,
        rd_err       => open,
        wr_ack       => open,
        wr_err       => open        
        );
end generate FIFO_GEN;

Read_data <= read_data_i;

-- Generate FIFO for ECC check bit data if C_INCLUDE_ECC_SUPPORT = 1
ECC_FIFO_GEN: if C_INCLUDE_ECC_SUPPORT = 1 generate

signal fifo_wren_ecc_gate : std_logic;
signal fifo_wren_ecc : std_logic;
signal fifo_rden_ecc : std_logic;
signal fifo_empty_ecc : std_logic;
signal ecc_chk_bits_rd_i : std_logic_vector (0 to NUM_ECC_BITS*2-1);

begin

    FIFO_WREN_ECC_GATE_PROCESS: process(Clk_ddr_rddata)
    begin
        if Clk_ddr_rddata'event and Clk_ddr_rddata = '1' then
            if DDR_read_data_en = '0' then
                fifo_wren_ecc_gate <= '0';
            elsif DDR_ReadDQS_ECC = '0' then
                fifo_wren_ecc_gate <= '1';
            end if;
        end if;
    end process FIFO_WREN_ECC_GATE_PROCESS;
    
    fifo_wren_ecc  <= '1' when (DDR_ReadDQS_ECC='1' and fifo_wren_ecc_gate='1') else '0';

    -- read the FIFO when not empty
    fifo_rden_ecc <= '1' when fifo_empty_ecc = '0' else '0';

    V2_ASYNCH_FIFO_I: async_fifo_v4_0
    generic map(
        c_enable_rlocs => 0,
        c_data_width => (NUM_ECC_BITS*2),
        c_fifo_depth => 15,
        c_has_almost_full => 0,
        c_has_almost_empty => 0,
        c_has_wr_count => 0,
        c_has_rd_count => 0,
        c_wr_count_width => 2,
        c_rd_count_width => 2,
        c_has_rd_ack => 0,
        c_rd_ack_low => 0,
        c_has_rd_err => 0,
        c_rd_err_low => 0,
        c_has_wr_ack => 0,
        c_wr_ack_low => 0,
        c_has_wr_err => 0,
        c_wr_err_low => 0,
        c_use_blockmem => 0
        )
    port map (
        din     => DDR_ReadData_ECC,
        wr_en   => fifo_wren_ecc,
        wr_clk  => Clk_ddr_rddata,
        rd_en   => fifo_rden_ecc,
        rd_clk  => Clk,
        ainit   => fifo_rst,
        dout    => ecc_chk_bits_rd_i,
        full    => open,
        empty   => fifo_empty_ecc,
        almost_full  => open,
        almost_empty => open,
        wr_count     => open,
        rd_count     => open,
        rd_ack       => open,
        rd_err       => open,
        wr_ack       => open,
        wr_err       => open 
        );

    ECC_chk_bits_rd <= ecc_chk_bits_rd_i;

end generate ECC_FIFO_GEN;

end imp;