📄 read_data_path2.vhd
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-------------------------------------------------------------------------------
-- $Id: read_data_path.vhd,v 1.1 2004/04/06 23:13:04 jennj Exp $
-------------------------------------------------------------------------------
-- read_data_path.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: read_data_path.vhd
-- Version: v1.10a
-- Description: This file contains the logic to synchronize the read data
-- for the DDR design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/15/02 First Version
--
-- ALS 06/07/02
-- ^^^^^^
-- Changed read data path to use an asynchronous FIFO to capture data and
-- re-align to internal FPGA clock
-- ~~~~~~
--
-- ALS 06/11/02
-- ^^^^^^
-- Since FDDRSE is only in Virtex2 and Virtex2P, don't need generate statements
-- for different FIFO types.
-- ~~~~~~
-- ALS 07/16/02
-- ^^^^^^
-- When C_INCLUDE_BURSTS=1, the IP2Bus_RdAck signal must precede the data by
-- one clock so the FIFO_EMPTY signal is negated and used to generate RdAck
-- without the register delay.
-- ~~~~~~
-- ALS 09/25/02
-- ^^^^^^
-- To allow for either pullups or pulldowns on DQS, will now register DQS on
-- both falling and rising edge of DDR clock and verify that it is 0 and then 1
-- before writing data to the FIFO
-- ~~~~~~
-- ALS 07/08/03
-- ^^^^^^
-- Removed instantiation of Coregen FIFO - instead modified code so that
-- XST would call Coregen to instantiate the FIFO.
-- ~~~~~~
-- JLJ 11/11/03
-- ^^^^^^
-- Version D: Add logic to support ECC check bit read registers. Add async FIFO
-- for ECC check bits.
-- ~~~~~~
-- JLJ 02/16/04
-- ^^^^^^
-- Remove C_INCLUDE_BURSTS generic parameter. Not being used.
-- ~~~~~~
-- JLJ 02/19/04
-- ^^^^^^
-- Use coregen_comp_defs to use package in proc_common_v2_00_a.
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.coregen_comp_defs.all;
use proc_common_v2_00_a.proc_common_pkg.all;
library unisim;
use unisim.all;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IPIF_DWIDTH -- width of the IPIF data bus
-- C_DDR_DWIDTH -- ddr data width
-- C_RDLAT_WIDTH -- determinate timer read latency counter width
-- C_RDLATCNT -- determinate timer read latency count
-- C_FAMILY -- target FPGA family type
-- NUM_ECC_BITS -- number of ECC check bits
--
-- Definition of Ports:
-- -- inputs
-- DDR_ReadData -- data input from DDR
-- DDR_ReadData_ECC -- check bit data input from DDR
-- DDR_ReadDQS -- data strobe input from DDR
-- DDR_ReadDQS_ECC -- ECC data strobe input from DDR
-- DDR_read_data_en -- gates the DDR input FIFO write enable
-- Read_data_en -- read data enable - used to reset FIFO
--
-- -- outputs
-- Read_data -- read data synchronized to FPGA clock
-- ECC_chk_bits_rd -- ECC check bit read data synchronized to FPGA clock
-- RdAck -- read data acknowledge
--
-- -- Clocks and reset
-- Clk -- bus clock
-- Clk_ddr_rddata -- DDR feedback clock shifted 90
-- Rst
---------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity read_data_path2 is
generic (
C_IPIF_DWIDTH : integer;
C_DDR_DWIDTH : integer;
C_FAMILY : string := "virtex2";
C_INCLUDE_ECC_SUPPORT : integer := 0;
NUM_ECC_BITS : integer
);
port (
ddr_test_cntl : in std_logic_vector(1 downto 0);
ddr_rd_bus : out std_logic_vector(19 downto 0);
DDR_ReadData : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
DDR_ReadData_ECC : in std_logic_vector(0 to NUM_ECC_BITS*2-1); -- ECC
DDR_ReadDQS : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_ReadDQS_ECC : in std_logic; -- ECC
DDR_read_data_en : in std_logic;
Read_data_en : in std_logic;
RdAck_rst : in std_logic;
Read_data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_rd : out std_logic_vector(0 to NUM_ECC_BITS*2-1); -- ECC
RdAck : out std_logic;
-- Clocks and reset
Clk : in std_logic;
Clk_ddr_rddata : in std_logic;
Rst : in std_logic
);
end entity read_data_path2;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of read_data_path2 is
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
constant ZERO_EMPTY : std_logic_vector(0 to C_IPIF_DWIDTH/16-1) := (others => '0');
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
-- fifo control signals
signal fifo_rden : std_logic;
signal fifo_wren : std_logic_vector(0 to C_IPIF_DWIDTH/16-1);
signal fifo_wren_gate : std_logic_vector(0 to C_IPIF_DWIDTH/16-1);
signal fifo_empty : std_logic_vector(0 to C_IPIF_DWIDTH/16-1);
signal fifo_rst : std_logic;
-- internal signals
signal read_data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal rdack_i : std_logic;
-------------------------------------------------------------------------------
-- DDR Read timeout signal
-------------------------------------------------------------------------------
signal dqs_tout_cnt : std_logic_vector(3 downto 0);
signal dqs_tout_flag : std_logic;
-------------------------------------------------------------------------------
-- Component declarations
-------------------------------------------------------------------------------
component ld_arith_reg
generic (
C_ADD_SUB_NOT : boolean := false;
C_REG_WIDTH : natural := 8;
C_RESET_VALUE : std_logic_vector;
C_LD_WIDTH : natural := 8;
C_LD_OFFSET : natural := 0;
C_AD_WIDTH : natural := 8;
C_AD_OFFSET : natural := 0
);
port (
CK : in std_logic;
RST : in std_logic;
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
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