#ddr_controller2.vhd#

xilinx ddr3最新VHDL代码,通过调试

        Write_data_ecc_mask => write_data_ecc_mask  , 
        Read_data_en        => read_data_en         ,
        DQ_oe_cmb           => dq_oe_cmb            , 
        DQ_ECC_oe_cmb       => dq_ecc_oe_cmb        ,
        DQS_oe              => dqs_oe               , 
        DQS_ECC_oe          => dqs_ecc_oe           , 
        DQS_rst             => dqs_rst              ,
        DQS_ECC_rst         => dqs_ecc_rst          ,
        DQS_setrst          => dqs_setrst           ,
        DQS_ECC_setrst      => dqs_ecc_setrst       ,
        CSn                 => csn                  , 
        RASn                => rasn                 , 
        CASn                => casn                 , 
        WEn                 => wen                  , 
        BankAddr            => bankaddr             , 
        Addr                => addr                 ,
        DDR_ReadData        => ddr_readdata         ,    
        DDR_ReadData_ECC    => ddr_readdata_ecc     ,
        DDR_read_data_en    => ddr_read_data_en     ,
        DDR_DQ_i            => DDR_DQ_i             ,
        DDR_DQ_o            => DDR_DQ_o             , 
        DDR_DQ_t            => DDR_DQ_t             , 
        DDR_DM              => DDR_DM               , 
        DDR_Read_DQS        => ddr_read_dqs         ,
        DDR_Read_DQS_ECC    => ddr_read_dqs_ecc     ,
        DDR_DQS_I           => DDR_DQS_i            ,
        DDR_DQS_o           => DDR_DQS_o            ,
        DDR_DQS_t           => DDR_DQS_t            ,        
        DDR_DM_ECC          => DDR_DM_ECC           ,
        DDR_DQ_ECC_o        => DDR_DQ_ECC_o         ,
        DDR_DQ_ECC_i        => DDR_DQ_ECC_i         ,
        DDR_DQ_ECC_t        => DDR_DQ_ECC_t         ,
        DDR_DQS_ECC_i       => DDR_DQS_ECC_i        ,
        DDR_DQS_ECC_o       => DDR_DQS_ECC_o        ,
        DDR_DQS_ECC_t       => DDR_DQS_ECC_t        ,        
        DDR_CSn             => DDR_CSn              , 
        DDR_RASn            => DDR_RASn             , 
        DDR_CASn            => DDR_CASn             , 
        DDR_WEn             => DDR_WEn              , 
        DDR_BankAddr        => DDR_BankAddr         , 
        DDR_Addr            => DDR_Addr             , 
        Clk                 => clk_i                , 
        Clk_n               => clk_n_i              , 
        Clk90               => clk90_i              , 
        Clk90_n             => clk90_n_i            , 
        Clk_ddr_rddata      => clk_ddr_rddata_i     ,
        Clk_ddr_rddata_n    => clk_ddr_rddata_n_i   ,
        Rst                 => rst              
        );

    IPIC_IF_I : entity ddr_v1_10_a.ipic_if(imp)
    generic map(
        C_NUM_BANKS_MEM     => C_NUM_BANKS_MEM,     -- integer
        C_DDR_AWIDTH        => C_DDR_AWIDTH,        -- integer
        C_DDR_DWIDTH        => C_DDR_DWIDTH,        -- integer
        C_DDR_COL_AWIDTH    => C_DDR_COL_AWIDTH,    -- integer
        C_DDR_BANK_AWIDTH   => C_DDR_BANK_AWIDTH,   -- integer
        C_IPIF_AWIDTH       => C_IPIF_AWIDTH,       -- integer
        C_IPIF_DWIDTH       => C_IPIF_DWIDTH,       -- integer
        C_INCLUDE_BURSTS    => C_INCLUDE_BURSTS,    -- integer
        C_INCLUDE_ECC_SUPPORT => C_INCLUDE_ECC_SUPPORT,
        NUM_ECC_BITS        => NUM_ECC_BITS
        )
    port map (
        Bus2IP_CS           => Bus2IP_CS   ,        -- in
        Bus2IP_Addr         => Bus2IP_Addr ,        -- in  (0:C_IPIF_AWIDTH-1)
        Bus2IP_Burst        => Bus2IP_Burst,        -- in
        Bus2IP_IBurst       => Bus2IP_IBurst,       -- in
        Bus2IP_Data         => Bus2IP_Data ,        -- in  (0:C_IPIF_DWIDTH-1)
        ECC_chk_bits_wr_in  => ECC_chk_bits_wr,     -- in  (0:NUM_ECC_BITS*2-1)
        Bus2IP_BE           => Bus2IP_BE   ,        -- in  (0:C_IPIF_DWIDTH/8-1)
        Bus2IP_RdReq        => Bus2IP_RdReq,        -- in
        Bus2IP_WrReq        => Bus2IP_WrReq,        -- in
        IP2Bus_ErrAck       => IP2Bus_ErrAck,       -- out
        IP2Bus_Retry        => IP2Bus_Retry,        -- out
        IP2Bus_Busy         => IP2Bus_Busy,         -- out
        IP2Bus_WrAddrAck    => IP2Bus_WrAddrAck,    -- out
        IP2Bus_RdAddrAck    => IP2Bus_RdAddrAck,    -- out
        IP2Bus_WrAck        => IP2Bus_WrAck,        -- out
        IP2Bus_RdAck        => IP2Bus_RdAck,        -- out
        IP2Bus_ToutSup      => IP2Bus_ToutSup,      -- out
        IP2Bus_data         => IP2Bus_data,         -- out (0:C_IPIF_DWIDTH-1)
        ECC_chk_bits_rd_out => ECC_chk_bits_rd,     -- out (0:NUM_ECC_BITS*2-1)
        Wr_AddrAck          => wr_addrack,          -- in
        Rd_AddrAck          => rd_addrack,          -- in
        WrAck               => wrack,               -- in
        RdAck               => rdack,               -- in
        ToutSup             => toutsup,             -- in
        Read_data           => read_data,           -- in  (0:C_IPIF_DWIDTH-1)
        ECC_chk_bits_rd_in  => ecc_rddata,          -- in  (0:NUM_ECC_BITS*2-1)
        Retry               => retry,               -- in
        Init_done           => init_done,           -- in
        Comb_Bus2IP_CS      => comb_Bus2IP_CS,      -- out
        IPIC_wrdata         => ipic_wrdata,         -- out (0:C_IPIF_DWIDTH-1)
        ECC_chk_bits_wr_out => ecc_wrdata,          -- out (0:NUM_ECC_BITS*2-1)
        IPIC_be             => ipic_be,             -- out (0:C_IPIF_DWIDTH/8-1)
        Burst               => burst,               -- out
        Reset_pendrdreq     => reset_pendrdreq,     -- in
        Reset_pendwrreq     => reset_pendwrreq,     -- in
        Row_addr            => row_addr,            -- out (0:C_DDR_AWIDTH-1)
        Col_addr            => col_addr,            -- out (0:C_DDR_AWIDTH-1)
        Bank_addr           => bank_addr,           -- out (0:C_DDR_BANK_AWIDTH-1)
        Pend_rdreq          => pend_rdreq,          -- out
        Pend_wrreq          => pend_wrreq,          -- out
        Same_row            => same_row,            -- out
        Same_bank           => same_bank,           -- out
        Clk                 => clk_i,               -- in
        Rst                 => rst                  -- in
        );

    RDDATA_PATH_I: read_data_path2
    generic map ( 
        C_IPIF_DWIDTH       => C_IPIF_DWIDTH,
        C_DDR_DWIDTH        => C_DDR_DWIDTH,
        C_FAMILY            => C_FAMILY,
        C_INCLUDE_ECC_SUPPORT => C_INCLUDE_ECC_SUPPORT,
        NUM_ECC_BITS        => NUM_ECC_BITS
        )
    port map (
        ddr_test_cntl       => ddr_test_cntl,
        ddr_rd_bus          => ddr_rd_bus           ,
        DDR_ReadData        => ddr_readdata         ,
        DDR_ReadData_ECC    => ddr_readdata_ecc     ,
        DDR_ReadDQS         => ddr_read_dqs         ,
        DDR_ReadDQS_ECC     => ddr_read_dqs_ecc     ,
        DDR_read_data_en    => ddr_read_data_en     ,
        Read_data_en        => read_data_en         ,
        RdAck_rst           => rdack_rst            ,
        Read_data           => read_data            ,
        ECC_chk_bits_rd     => ecc_rddata           ,
        RdAck               => rdack                ,
        Clk                 => clk_i                ,
        Clk_ddr_rddata      => clk_ddr_rddata_i     ,
        Rst                 => Rst
        );

end generate W_ECC;


-------------------------------------------------------------------
-- No ECC logic to be instantiated/supported
-- when C_INCLUDE_ECC_SUPPORT = 0.
-------------------------------------------------------------------
WO_ECC: if C_INCLUDE_ECC_SUPPORT = 0 generate

constant ZERO_ECC_BITS      : std_logic_vector(0 to NUM_ECC_BITS*2-1)    := (others => '0');
constant ZERO_DQ_ECC_BITS   : std_logic_vector(0 to NUM_ECC_BITS-1)      := (others => '0');
constant ZERO_ECC_MASK      : std_logic_vector(0 to C_IPIF_DWIDTH/32-1)  := (others => '1');

begin
    
    COMMAND_STATEMACHINE_I : entity ddr_v1_10_a.command_statemachine(imp)
    generic map (
        C_DDR_AWIDTH            => C_DDR_AWIDTH,                    -- integer
        C_DDR_DWIDTH            => C_DDR_DWIDTH,                    -- integer
        C_DDR_COL_AWIDTH        => C_DDR_COL_AWIDTH,                -- integer
        C_DDR_BANK_AWIDTH       => C_DDR_BANK_AWIDTH,               -- integer
        C_REG_DIMM              => C_REG_DIMM,                      -- integer
        C_MRDCNT                => MRDCNT,         
        C_RFCCNT                => RFCCNT,         
        C_RCDCNT                => RCDCNT,         
        C_RPCNT                 => RPCNT,          
        C_GP_CNTR_WIDTH         => GPCNT_WIDTH,                     -- integer
        C_OPB_BUS               => C_OPB_BUS,                       -- integer
        C_PLB_BUS               => C_PLB_BUS,                       -- integer
        C_INCLUDE_BURSTS        => C_INCLUDE_BURSTS,                -- integer
        C_INCLUDE_ECC_SUPPORT   => C_INCLUDE_ECC_SUPPORT,           -- integer
        C_NUM_BANKS_MEM         => C_NUM_BANKS_MEM                  -- integer
        )
    port map (
        Comb_Bus2IP_CS  => comb_Bus2IP_CS,    -- in
        Bus2IP_CS       => Bus2IP_CS,         -- in
        Row_addr        => row_addr,          -- in  (0:C_DDR_AWIDTH-1)
        Col_addr        => col_addr,          -- in  (0:C_DDR_AWIDTH-1)
        Bank_addr       => bank_addr,         -- in  (0:C_DDR_BANK_AWIDTH-1)
        Bus2IP_RdReq    => Bus2IP_RdReq,      -- in
        Bus2IP_WrReq    => Bus2IP_WrReq,      -- in 
        Pend_rdreq      => pend_rdreq,        -- in
        Pend_wrreq      => pend_wrreq,        -- in
        Same_row        => same_row,          -- in
        Same_bank       => same_bank,         -- in
        Read_dqs_ce     => read_dqs_ce,       -- out
        Retry           => retry,             -- out
        Rd_AddrAck      => rd_addrack,        -- out
        Wr_AddrAck      => wr_addrack,        -- out
        Reset_pendrdreq => reset_pendrdreq,   -- out
        Reset_pendwrreq => reset_pendwrreq,   -- out
        ToutSup         => toutsup,           -- out
        Refresh         => refresh,           -- in
        Precharge       => precharge,         -- in
        Load_mr         => load_mr,           -- in
        Register_data   => register_data,     -- in  (0:C_DDR_AWIDTH-1)
        Register_sel    => register_sel,      -- in  (0:C_DDR_BANK_AWIDTH-1)
        Init_done       => init_done,         -- in
        Cmd_done        => cmd_done,          -- out
        Read_data_done  =>  read_data_done,   -- in 
        Read_data_done_rst  =>  read_data_done_rst, -- out    
        Pend_write      => pend_write,        -- out
        Pend_read       => pend_read,         -- out
        Read_pause      => read_pause,        -- out
        Trefi_end       => trefi_pwrup_end,   -- in
        Trc_end         => trc_end,           -- in
        Trrd_end        => trrd_end,          -- in
        Tras_end        => tras_end,          -- in
        Twr_end         => twr_end,           -- in
        GPcnt_end       => gpcnt_end,         -- in
        Tcmd_end        => tcmd_end,          -- in
        Twr_rst         => twr_rst,           -- out
        Tcmd_load       => tcmd_load,         -- out
        Tcmd_cnt_en     => tcmd_cnt_en,       -- out
        Trefi_load      => trefi_load,        -- out
        Trc_load        => trc_load,          -- out
        Trrd_load       => trrd_load,         -- out
        Tras_load       => tras_load,         -- out
        GPcnt_load      => gpcnt_load,        -- out
        GPcnt_en        => gpcnt_en,          -- out
        GPcnt_data      => gpcnt_data,        -- out (0:C_GP_CNTR_WIDTH-1)
        DDR_CSn         => csn,               -- out (0:C_NUM_BANKS_MEM-1)
        DDR_RASn        => rasn,              -- out
        DDR_CASn        => casn,              -- out
        DDR_WEn         => wen,               -- out
        DDR_Addr        => addr,              -- out (0:C_DDR_AWIDTH-1)
        DDR_BankAddr    => bankaddr,          -- out (0:C_DDR_BANK_AWIDTH-1)
        DQ_oe_cmb       => dq_oe_cmb,         -- out
        DQS_oe          => dqs_oe,            -- out
        DQS_rst         => dqs_rst,           -- out
        DQS_setrst      => dqs_setrst,        -- out
        DQ_ECC_oe_cmb   => open,              -- out
        DQS_ECC_oe      => open,              -- out
        DQS_ECC_rst     => open,              -- out
        DQS_ECC_setrst  => open,              -- out
        Clk             => clk_i,             -- in
        Rst             => rst                -- in
        );

    DATASM_I: entity ddr_v1_10_a.data_statemachine(imp) 
    generic map ( 
        C_DDR_DWIDTH            => C_DDR_DWIDTH,
        C_IPIF_DWIDTH           => C_IPIF_DWIDTH,
        C_REG_DIMM              => C_REG_DIMM,
        C_INCLUDE_BURSTS        => C_INCLUDE_BURSTS,                -- integer
        C_INCLUDE_ECC_SUPPORT   => C_INCLUDE_ECC_SUPPORT,           -- integer
        NUM_ECC_BITS            => NUM_ECC_BITS
        )
    port map (
        IPIC_wrdata         =>  ipic_wrdata         , 
        ECC_chk_bits_wr     =>  ZERO_ECC_BITS       ,
        IPIC_be             =>  ipic_be             ,
        Bus2IP_Burst        =>  burst               ,
        Comb_Bus2IP_CS      =>  comb_Bus2IP_CS      ,
        Pend_write          =>  pend_write          ,                                            
        Pend_read           =>  pend_read           ,                                            
        DDR_brst_end        =>  ddr_brst_end        ,                                            
        Tcaslat_end         =>  tcaslat_