#ddr_controller2.vhd#

xilinx ddr3最新VHDL代码,通过调试

    Register_sel        =>   register_sel       , 
    Init_done           =>   init_done          ,
    DDR_CKE             =>   DDR_CKE            ,
    Clk                 =>   clk_i              ,                                           
    Rst                 =>   Rst                                                            
    );

CNTRS_I: entity ddr_v1_10_a.counters(imp) 
generic map ( 
    C_GPCNT_WIDTH           =>  GPCNT_WIDTH     ,
    C_RCCNT_WIDTH           =>  RCCNT_WIDTH     ,
    C_RRDCNT_WIDTH          =>  RRDCNT_WIDTH    ,
    C_RASCNT_WIDTH          =>  RASCNT_WIDTH    ,
    C_REFICNT_WIDTH         =>  REFICNT_WIDTH   ,
    C_WRCNT_WIDTH           =>  WRCNT_WIDTH     ,
    C_BRSTCNT_WIDTH         =>  BRSTCNT_WIDTH   ,
    C_CASLATCNT_WIDTH       =>  CASLATCNT_WIDTH ,
    C_RCCNT                 =>  RCCNT           ,
    C_RRDCNT                =>  RRDCNT           ,
    C_RASCNT                =>  RASCNT          ,
    C_REFICNT               =>  REFICNT         ,
    C_200US_CNT             =>  CNT_200US       ,
    C_200CK_CNT             =>  CNT_200CLK      ,
    C_WRCNT                 =>  WRCNT           ,
    C_BRSTCNT               =>  BRSTCNT         ,
    C_CMDCNT                =>  CMDCNT          ,
    C_CASLATCNT             =>  CASLATCNT       ,
    C_DDR_BRST_SIZE         =>  C_DDR_BRST_SIZE ,
    C_CASLAT                =>  C_DDR_CAS_LAT+C_REG_DIMM                
    )
port map (
    GPcnt_load              => gpcnt_load        ,                                           
    GPcnt_en                => gpcnt_en          ,                                           
    GPcnt_data              => gpcnt_data        ,                                           
    Trc_load                => trc_load          ,                                           
    Trrd_load               => trrd_load         ,                                           
    Tras_load               => tras_load         ,                                           
    Trefi_load              => trefi_load        ,                                           
    Tpwrup_load             => tpwrup_load       ,                                           
    Tbrst_load              => tbrst_load        ,                                           
    Tbrst_cnt_en            => tbrst_cnt_en      , 
    Init_done               => init_done         ,
    Tcmd_load               => tcmd_load         ,
    Tcmd_cnt_en             => tcmd_cnt_en       ,
    Tcaslat_load            => tcaslat_load      ,
    Tcaslat_cnt_en          => tcaslat_cnt_en    ,
    Twr_load                => twr_load          ,
    Twr_rst                 => twr_rst           ,
    Twr_cnten               => twr_cnten         ,
    GPcnt_end               => gpcnt_end         ,                                           
    Trc_end                 => trc_end           ,                                           
    Trrd_end                => trrd_end          ,                                           
    Tras_end                => tras_end          ,                                           
    Trefi_pwrup_end         => trefi_pwrup_end   ,                                           
    Twr_end                 => twr_end           ,                                           
    DDR_brst_end            => ddr_brst_end      ,
    Tcmd_end                => tcmd_end          ,
    Tcaslat_end             => tcaslat_end       ,
    Clk                     => clk_i             ,                                           
    Rst                     => Rst                                                           
    );

CLKGEN_I: entity ddr_v1_10_a.clock_gen(imp) 
generic map ( 
    C_NUM_CLK_PAIRS     =>  C_NUM_CLK_PAIRS     ,
    C_FAMILY            =>  C_FAMILY
    )
port map (
    -- sys_rst             =>  rst,
    Sys_clk             =>  Sys_clk,             
    Sys_clk_n           =>  Sys_clk_n,             
    Clk90_in            =>  Clk90_in,             
    Clk90_in_n          =>  Clk90_in_n,             
    DDR_Clk90_in        =>  DDR_Clk90_in,             
    DDR_Clk90_in_n      =>  DDR_Clk90_in_n,             
    Clk                 =>  clk_i,             
    Clk_n               =>  clk_n_i,             
    Clk90               =>  clk90_i,                      
    Clk90_n             =>  clk90_n_i,                      
    Clk_ddr_rddata      =>  clk_ddr_rddata_i,             
    Clk_ddr_rddata_n    =>  clk_ddr_rddata_n_i,             
    DDR_Clk             =>  DDR_Clk,                     
    DDR_Clkn            =>  DDR_Clkn                  
    );
    
-------------------------------------------------------------------
-- Support registers and port connections for generating ECC logic
-- when C_INCLUDE_ECC_SUPPORT = 1.
-------------------------------------------------------------------
W_ECC: if C_INCLUDE_ECC_SUPPORT = 1 generate

-- Only create signals if C_INCLUDE_ECC_SUPPORT = 1
signal write_data_ecc       : std_logic_vector(0 to NUM_ECC_BITS*2-1);
signal write_data_ecc_mask  : std_logic_vector (0 to C_IPIF_DWIDTH/32-1);
signal write_data_ecc_en    : std_logic;
signal write_dqs_ecc_en     : std_logic;
signal dqs_ecc_rst          : std_logic;
signal dqs_ecc_setrst       : std_logic;
signal dqs_ecc_oe           : std_logic;
signal dq_ecc_oe_cmb        : std_logic;
signal ddr_readdata_ecc     : std_logic_vector(0 to NUM_ECC_BITS*2-1);
signal ddr_read_dqs_ecc     : std_logic;
signal ecc_wrdata, ecc_rddata : std_logic_vector(0 to NUM_ECC_BITS*2-1);

begin

    COMMAND_STATEMACHINE_I : entity ddr_v1_10_a.command_statemachine(imp)
    generic map (
        C_DDR_AWIDTH        => C_DDR_AWIDTH,              -- integer
        C_DDR_DWIDTH        => C_DDR_DWIDTH,              -- integer
        C_DDR_COL_AWIDTH    => C_DDR_COL_AWIDTH,          -- integer
        C_DDR_BANK_AWIDTH   => C_DDR_BANK_AWIDTH,         -- integer
        C_REG_DIMM          => C_REG_DIMM,                -- integer
        C_MRDCNT            => MRDCNT,         
        C_RFCCNT            => RFCCNT,         
        C_RCDCNT            => RCDCNT,         
        C_RPCNT             => RPCNT,          
        C_GP_CNTR_WIDTH     => GPCNT_WIDTH,               -- integer
        C_OPB_BUS           => C_OPB_BUS,                 -- integer
        C_PLB_BUS           => C_PLB_BUS,                 -- integer
        C_INCLUDE_BURSTS      => C_INCLUDE_BURSTS,        -- integer
        C_INCLUDE_ECC_SUPPORT => C_INCLUDE_ECC_SUPPORT,
        C_NUM_BANKS_MEM       => C_NUM_BANKS_MEM          -- integer
        )
    port map (
        Comb_Bus2IP_CS  => comb_Bus2IP_CS,    -- in
        Bus2IP_CS       => Bus2IP_CS,         -- in
        Row_addr        => row_addr,          -- in  (0:C_DDR_AWIDTH-1)
        Col_addr        => col_addr,          -- in  (0:C_DDR_AWIDTH-1)
        Bank_addr       => bank_addr,         -- in  (0:C_DDR_BANK_AWIDTH-1)
        Bus2IP_RdReq    => Bus2IP_RdReq,      -- in
        Bus2IP_WrReq    => Bus2IP_WrReq,      -- in 
        Pend_rdreq      => pend_rdreq,        -- in
        Pend_wrreq      => pend_wrreq,        -- in
        Same_row        => same_row,          -- in
        Same_bank       => same_bank,         -- in
        Read_dqs_ce     => read_dqs_ce,       -- out
        Retry           => retry,             -- out
        Rd_AddrAck      => rd_addrack,        -- out
        Wr_AddrAck      => wr_addrack,        -- out
        Reset_pendrdreq => reset_pendrdreq,   -- out
        Reset_pendwrreq => reset_pendwrreq,   -- out
        ToutSup         => toutsup,           -- out
        Refresh         => refresh,           -- in
        Precharge       => precharge,         -- in
        Load_mr         => load_mr,           -- in
        Register_data   => register_data,     -- in  (0:C_DDR_AWIDTH-1)
        Register_sel    => register_sel,      -- in  (0:C_DDR_BANK_AWIDTH-1)
        Init_done       => init_done,         -- in
        Cmd_done        => cmd_done,          -- out
        Read_data_done  =>  read_data_done,   -- in 
        Read_data_done_rst  =>  read_data_done_rst, -- out    
        Pend_write      => pend_write,        -- out
        Pend_read       => pend_read,         -- out
        Read_pause      => read_pause,        -- out
        Trefi_end       => trefi_pwrup_end,   -- in
        Trc_end         => trc_end,           -- in
        Trrd_end        => trrd_end,          -- in
        Tras_end        => tras_end,          -- in
        Twr_end         => twr_end,           -- in
        GPcnt_end       => gpcnt_end,         -- in
        Tcmd_end        => tcmd_end,          -- in
        Twr_rst         => twr_rst,           -- out
        Tcmd_load       => tcmd_load,         -- out
        Tcmd_cnt_en     => tcmd_cnt_en,       -- out
        Trefi_load      => trefi_load,        -- out
        Trc_load        => trc_load,          -- out
        Trrd_load       => trrd_load,         -- out
        Tras_load       => tras_load,         -- out
        GPcnt_load      => gpcnt_load,        -- out
        GPcnt_en        => gpcnt_en,          -- out
        GPcnt_data      => gpcnt_data,        -- out (0:C_GP_CNTR_WIDTH-1)
        DDR_CSn         => csn,               -- out (0:C_NUM_BANKS_MEM-1)
        DDR_RASn        => rasn,              -- out
        DDR_CASn        => casn,              -- out
        DDR_WEn         => wen,               -- out
        DDR_Addr        => addr,              -- out (0:C_DDR_AWIDTH-1)
        DDR_BankAddr    => bankaddr,          -- out (0:C_DDR_BANK_AWIDTH-1)
        DQ_oe_cmb       => dq_oe_cmb,         -- out
        DQS_oe          => dqs_oe,            -- out
        DQS_rst         => dqs_rst,           -- out
        DQS_setrst      => dqs_setrst,        -- out
        DQ_ECC_oe_cmb   => dq_ecc_oe_cmb,     -- out
        DQS_ECC_oe      => dqs_ecc_oe,        -- out
        DQS_ECC_rst     => dqs_ecc_rst,       -- out
        DQS_ECC_setrst  => dqs_ecc_setrst,    -- out
        Clk             => clk_i,             -- in
        Rst             => rst                -- in
        );

    DATASM_I: entity ddr_v1_10_a.data_statemachine(imp) 
    generic map ( 
        C_DDR_DWIDTH    => C_DDR_DWIDTH,
        C_IPIF_DWIDTH   => C_IPIF_DWIDTH,
        C_REG_DIMM      => C_REG_DIMM,
        C_INCLUDE_BURSTS    => C_INCLUDE_BURSTS,    -- integer
        C_INCLUDE_ECC_SUPPORT => C_INCLUDE_ECC_SUPPORT,
        NUM_ECC_BITS    => NUM_ECC_BITS 
        )
    port map (
        IPIC_wrdata         =>  ipic_wrdata         , 
        ECC_chk_bits_wr     =>  ecc_wrdata          ,
        IPIC_be             =>  ipic_be             ,
        Bus2IP_Burst        =>  burst               ,
        Comb_Bus2IP_CS      =>  comb_Bus2IP_CS      ,
        Pend_write          =>  pend_write          ,                                            
        Pend_read           =>  pend_read           ,                                            
        DDR_brst_end        =>  ddr_brst_end        ,                                            
        Tcaslat_end         =>  tcaslat_end         ,
        Twr_end             =>  twr_end             ,                                           
        Read_data_done_rst  =>  read_data_done_rst  ,
        Read_pause          =>  read_pause          ,       
        RdAck               =>  rdack               ,            
        WrAck               =>  WrAck               ,                                            
        Read_data_en        =>  read_data_en        ,
        Write_data_en       =>  write_data_en       ,
        Write_data_ecc_en   =>  write_data_ecc_en   ,
        Write_dqs_en        =>  write_dqs_en        ,
        Write_dqs_ecc_en    =>  write_dqs_ecc_en    ,
        Write_data          =>  write_data          ,
        Write_data_ecc      =>  write_data_ecc      ,
        Write_data_mask     =>  write_data_mask     ,
        Write_data_ecc_mask =>  write_data_ecc_mask ,
        Read_data_done      =>  read_data_done      , 
        Tbrst_cnt_en        =>  tbrst_cnt_en        ,
        Tbrst_load          =>  tbrst_load          ,
        Tcaslat_load        =>  tcaslat_load        ,
        Tcaslat_cnt_en      =>  tcaslat_cnt_en      ,
        Twr_load            =>  twr_load            ,
        Twr_cnten           =>  twr_cnten           ,
        RdAck_rst           =>  rdack_rst           ,
        Clk                 =>  clk_i               ,                                                        
        Rst                 =>  Rst                                                        
        );

    IO_REG_I: io_registers2 
    generic map ( 
        C_DDR_AWIDTH            => C_DDR_AWIDTH,
        C_DDR_BANK_AWIDTH       => C_DDR_BANK_AWIDTH,  
        C_DDR_DWIDTH            => C_DDR_DWIDTH,       
        C_IPIF_DWIDTH           => C_IPIF_DWIDTH,
        C_FAMILY                => C_FAMILY,
        C_INCLUDE_ECC_SUPPORT   => C_INCLUDE_ECC_SUPPORT,
        NUM_ECC_BITS            => NUM_ECC_BITS,
        C_NUM_BANKS_MEM         => C_NUM_BANKS_MEM  
        )
    port map ( 
        Write_data          => write_data           ,
        Write_data_ecc      => write_data_ecc       ,
        Write_data_en       => write_data_en        , 
        Write_data_ecc_en   => write_data_ecc_en    , 
        Write_dqs_en        => write_dqs_en         ,
        Write_dqs_ecc_en    => write_dqs_ecc_en     ,
        Read_dqs_ce         => read_dqs_ce          ,
        Write_data_mask     => write_data_mask      ,