#ddr_controller2.vhd#

xilinx ddr3最新VHDL代码,通过调试

function max(indata : INTEGER_ARRAY ) return integer is
  variable max_val : integer;
begin
  max_val := 0;
  for i in 0 to indata'length-1 loop
    if indata(i) > max_val then
        max_val := indata(i);
    end if;
 end loop;
  
 return max_val; 
end max;

--
-- Function get_init_clocks returns the number of clocks for the initialization
-- time. If simulation, the initialization time is set by C_SIM_INIT_TIME_PS.
-- Otherwise, it is 200us.
--
function get_init_clocks return integer is
    variable init_clocks : integer;




begin

    -- the following assignment is used in synthesis
    init_clocks := ((200000000-1)/C_CLK_PERIOD)+1;
    
    -- the following assignment is used in simulation
    -- synthesis translate off
    init_clocks := ((C_SIM_INIT_TIME_PS-1)/C_CLK_PERIOD)+1;
    -- synthesis translate on
    
    return init_clocks;
end get_init_clocks;

-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
-- create integer values of the delay parameters divided by clock frequency
-- to round values to next integer
constant DDR_TMRD_CLKS   : integer range 1 to 31 := ((C_DDR_TMRD-1)/C_CLK_PERIOD)+1;
constant DDR_TWR_CLKS    : integer range 1 to 31 := ((C_DDR_TWR-1)/C_CLK_PERIOD)+1;
constant DDR_TRAS_CLKS   : integer range 1 to 31 := ((C_DDR_TRAS-1)/C_CLK_PERIOD)+1;
constant DDR_TRC_CLKS    : integer range 1 to 31 := ((C_DDR_TRC-1)/C_CLK_PERIOD)+1;
constant DDR_TRFC_CLKS   : integer range 1 to 31 := ((C_DDR_TRFC-1)/C_CLK_PERIOD)+1;
constant DDR_TRCD_CLKS   : integer range 1 to 31 := ((C_DDR_TRCD-1)/C_CLK_PERIOD)+1;
constant DDR_TRRD_CLKS   : integer range 1 to 31 := ((C_DDR_TRRD-1)/C_CLK_PERIOD)+1;
constant DDR_TREFC_CLKS  : integer := ((C_DDR_TREFC-1)/C_CLK_PERIOD)+1;
constant DDR_TREFI_CLKS  : integer := ((C_DDR_TREFI-1)/C_CLK_PERIOD)+1;
constant DDR_TRP_CLKS    : integer range 1 to 31 := ((C_DDR_TRP-1)/C_CLK_PERIOD)+1;

-- set the number of clocks for the 200uS counter to the generic C_SIM_INIT_TIME_PS
-- for simulation by calling function get_init_clocks
constant CNT_200US_CLKS  : integer := get_init_clocks;

--                                    
-- set width of counters
--
constant RCCNT_WIDTH    : integer := max2(1,log2(DDR_TRC_CLKS));
constant RRDCNT_WIDTH   : integer := max2(1,log2(DDR_TRRD_CLKS));
constant RASCNT_WIDTH   : integer := max2(1,log2(DDR_TRAS_CLKS));

-- width of the REFI and initialization counter is the max of the number of clocks for
-- REFI and initialization (sim_init_time or 200us and 200 clks)
constant INITCNTR_WIDTH : integer := max2(log2(CNT_200US_CLKS+1),log2(200));
constant REFICNT_WIDTH  : integer := max2(log2(DDR_TREFI_CLKS),INITCNTR_WIDTH);

constant BRSTCNT_WIDTH  : integer := max2(1,log2(C_DDR_BRST_SIZE/2)); 
constant WRCNT_WIDTH    : integer := max2(1,log2(DDR_TWR_CLKS));

-- add one to CAS latency if C_REG_DIMM
constant CASLATCNT_WIDTH: integer := max2(1,log2(C_DDR_CAS_LAT+C_REG_DIMM));

-- general purpose counter is used to count Tmrd, Trfc, Trp and Trcd
-- set this counter width from the max of these values
constant CNTR_WIDTH     : INTEGER_ARRAY := ( max2(1,log2(DDR_TMRD_CLKS)), 
                                             max2(1,log2(DDR_TRFC_CLKS)),
                                             max2(1,log2(DDR_TRP_CLKS)),
                                             max2(1,log2(DDR_TRCD_CLKS)));
                                             
constant GPCNT_WIDTH    : integer := max(CNTR_WIDTH);

--
-- create std_logic_vectors for counter load values
--
constant RCCNT          : std_logic_vector(0 to RCCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRC_CLKS-1, RCCNT_WIDTH);
constant RRDCNT         : std_logic_vector(0 to RRDCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRRD_CLKS-1, RRDCNT_WIDTH);
constant RASCNT         : std_logic_vector(0 to RASCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRAS_CLKS-1, RASCNT_WIDTH);
-- Set REFICNT to DDR_TREFI_CLKS - X where X is enough margin 
-- to do a refresh properly knowing that the state machine may be in another command
constant REF_MARGIN     : integer   := 64;
constant REFICNT        : std_logic_vector(0 to REFICNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TREFI_CLKS-REF_MARGIN-1, REFICNT_WIDTH);
constant WRCNT          : std_logic_vector(0 to WRCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TWR_CLKS-1, WRCNT_WIDTH);
constant BRSTCNT        : std_logic_vector(0 to BRSTCNT_WIDTH-1) :=
                        conv_std_logic_vector(C_DDR_BRST_SIZE/2-1, BRSTCNT_WIDTH);
-- determine brstcnt/2 to mark when new command can be applied 
constant CMDCNT        : std_logic_vector(0 to BRSTCNT_WIDTH-1) :=
                        conv_std_logic_vector(C_DDR_BRST_SIZE/2-1, BRSTCNT_WIDTH);

-- add one to CAS latency if C_REG_DIMM
constant CASLATCNT      : std_logic_vector(0 to CASLATCNT_WIDTH-1) :=
                        conv_std_logic_vector(C_DDR_CAS_LAT+C_REG_DIMM-1, CASLATCNT_WIDTH);
constant CNT_200US      : std_logic_vector(0 to REFICNT_WIDTH-1) :=
                        conv_std_logic_vector(CNT_200US_CLKS-1, REFICNT_WIDTH);
constant CNT_200CLK     : std_logic_vector(0 to REFICNT_WIDTH-1) :=
                        conv_std_logic_vector(200-1, REFICNT_WIDTH);

constant MRDCNT         : std_logic_vector(0 to GPCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TMRD_CLKS-1, GPCNT_WIDTH);
constant RFCCNT         : std_logic_vector(0 to GPCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRFC_CLKS-1, GPCNT_WIDTH);
constant RPCNT          : std_logic_vector(0 to GPCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRP_CLKS-1, GPCNT_WIDTH);
constant RCDCNT         : std_logic_vector(0 to GPCNT_WIDTH-1) :=
                        conv_std_logic_vector(DDR_TRCD_CLKS-1, GPCNT_WIDTH);

-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal gpcnt_load           : std_logic;
signal gpcnt_en             : std_logic;
signal gpcnt_data           : std_logic_vector(0 to GPCNT_WIDTH-1);
signal trc_load             : std_logic;
signal trrd_load            : std_logic;
signal tras_load            : std_logic;
signal trefi_load           : std_logic;
signal tpwrup_load          : std_logic;
signal tbrst_load           : std_logic;
signal tbrst_cnt_en         : std_logic;
signal tcmd_load            : std_logic;
signal tcmd_cnt_en          : std_logic;
signal tcaslat_load         : std_logic;
signal tcaslat_cnt_en       : std_logic;
signal tcaslat_end          : std_logic;
signal gpcnt_end            : std_logic;
signal trc_end              : std_logic;
signal trrd_end             : std_logic;
signal tras_end             : std_logic;
signal trefi_pwrup_end      : std_logic;       
signal twr_load             : std_logic;
signal twr_rst              : std_logic;
signal twr_cnten            : std_logic;
signal twr_end              : std_logic;
signal ddr_brst_end         : std_logic;  
signal tcmd_end             : std_logic;

signal refresh              : std_logic;
signal precharge            : std_logic;
signal load_mr              : std_logic;
signal register_data        : std_logic_vector(0 to C_DDR_AWIDTH-1);
signal register_sel         : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
signal cmd_done             : std_logic;  
signal init_done            : std_logic;

signal read_data_done       : std_logic;
signal read_data_done_rst   : std_logic;
signal ipic_be              : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal ipic_wrdata          : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal write_data           : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal write_data_mask      : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal write_data_en        : std_logic;
signal write_dqs_en         : std_logic_vector(0 to C_DDR_DWIDTH/8-1);
signal dq_oe_cmb            : std_logic;
signal dqs_oe               : std_logic_vector(0 to C_DDR_DWIDTH/8-1);
signal dqs_rst              : std_logic_vector(0 to C_DDR_DWIDTH/8-1);
signal dqs_setrst           : std_logic_vector(0 to C_DDR_DWIDTH/8-1);
signal read_data_en         : std_logic;
signal ddr_readdata         : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal ddr_read_data_en     : std_logic;
signal ddr_read_dqs         : std_logic_vector(0 to C_DDR_DWIDTH/8-1);
signal read_data            : std_logic_vector(0 to C_IPIF_DWIDTH-1);

signal rdack                : std_logic;
signal rdack_rst            : std_logic;
signal read_pause           : std_logic;
signal wrack                : std_logic;
signal retry                : std_logic;
signal rd_addrack           : std_logic;
signal wr_addrack           : std_logic;
signal read_dqs_ce          : std_logic;
signal burst                : std_logic;

signal row_addr             : std_logic_vector(0 to C_DDR_AWIDTH-1);
signal col_addr             : std_logic_vector(0 to C_DDR_AWIDTH-1);
signal bank_addr            : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
signal pend_rdreq           : std_logic;
signal pend_wrreq           : std_logic;
signal same_row             : std_logic;
signal same_bank            : std_logic;
signal reset_pendrdreq      : std_logic;
signal reset_pendwrreq      : std_logic;
signal toutsup              : std_logic;
signal pend_read            : std_logic;
signal pend_write           : std_logic;

signal csn                  : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal rasn                 : std_logic;
signal casn                 : std_logic;
signal wen                  : std_logic;
signal addr                 : std_logic_vector(0 to C_DDR_AWIDTH-1);
signal bankaddr             : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);

signal clk_i                : std_logic;
signal clk_n_i              : std_logic;
signal clk90_i              : std_logic;
signal clk90_n_i            : std_logic;
signal clk_ddr_rddata_i     : std_logic;
signal clk_ddr_rddata_n_i   : std_logic;

signal comb_Bus2IP_CS       : std_logic;

signal ddr_rd_bus           : std_logic_vector(19 downto 0);

-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------

-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------


begin  -- architecture imp

-- assign output signals
DDR_Init_done <= init_done;

-------------------------------------------------------------------------------
-- Component Instantiations
-------------------------------------------------------------------------------

-- Same component instantiation regardless of C_INCLUDE_ECC_SUPPORT
INITSM_I: entity ddr_v1_10_a.init_statemachine(imp) 
generic map ( 
    C_NUM_BANKS_MEM     =>  C_NUM_BANKS_MEM     ,
    C_DDR_AWIDTH        =>  C_DDR_AWIDTH        ,    
    C_DDR_BANK_AWIDTH   =>  C_DDR_BANK_AWIDTH   ,    
    C_DDR_BRST_SIZE     =>  C_DDR_BRST_SIZE     ,    
    C_DDR_CAS_LAT       =>  C_DDR_CAS_LAT
    )
port map(
    Cmd_done            =>   cmd_done           ,                                           
    Trefi_pwrup_end     =>   trefi_pwrup_end    ,                                           
    Precharge           =>   precharge          ,                                           
    Load_mr             =>   load_mr            ,                                           
    Tpwrup_load         =>   tpwrup_load        ,                                           
    Refresh             =>   refresh            ,                                           
    Register_data       =>   register_data      ,