#ddr_controller2.vhd#

xilinx ddr3最新VHDL代码,通过调试

--    DDR_WEn                   -- DDR write enable
--    DDR_DM                    -- DDR data mask
--    DDR_BankAddr              -- DDR bank address
--    DDR_Addr                  -- DDR address
--    DDR_DQ_o                  -- DDR DQ output
--    DDR_DQ_i                  -- DDR DQ input
--    DDR_DQ_t                  -- DDR DQ output enable
--    DDR_DQS_i                 -- DDR DQS input
--    DDR_DQS_o                 -- DDR DQS output
--    DDR_DQS_t                 -- DDR DQS output enable
--    DDR_DM_ECC                -- DDR ECC data mask (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQ_ECC_o              -- DDR ECC DQ output (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQ_ECC_i              -- DDR ECC DQ input (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQ_ECC_t              -- DDR ECC DQ output enable (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQS_ECC_i             -- DDR ECC DQS input (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQS_ECC_o             -- DDR ECC DQS output (when C_INCLUDE_ECC_SUPPORT=1)
--    DDR_DQS_ECC_t             -- DDR ECC DQS output enable (when C_INCLUDE_ECC_SUPPORT=1)
--    
--    -- Clocks and reset
--    Sys_Clk                   -- PLB clock 
--    Sys_Clk_n                 -- PLB clock shifted by 180
--    Clk90_in                  -- PLB clock shifted 90
--    Clk90_in_n                -- PLB clock shifted by 270
--    DDR_Clk90_in              -- DDR clock feedback shifted 90
--    DDR_Clk90_in_n            -- DDR clock feedback shifted by 270
--    Rst                       -- System reset
---------------------------------------------------------------------------

-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------

entity ddr_controller2 is
    generic (
        C_FAMILY                : string   := "virtex2";
        C_NUM_BANKS_MEM         : integer range 1 to 4 := 1;
        C_NUM_CLK_PAIRS         : integer range 1 to 4 := 1;
        C_REG_DIMM              : integer  := 0;
        C_DDR_TMRD              : integer  := 15000;
        C_DDR_TWR               : integer  := 15000;
        C_DDR_TWTR              : integer  := 1;
        C_DDR_TRAS              : integer  := 40000;
        C_DDR_TRC               : integer  := 65000;
        C_DDR_TRFC              : integer  := 75000;
        C_DDR_TRCD              : integer  := 20000;
        C_DDR_TRRD              : integer  := 15000;
        C_DDR_TREFC             : integer  := 70000000;
        C_DDR_TREFI             : integer  := 7800000;
        C_DDR_TRP               : integer  := 20000;
        C_DDR_CAS_LAT           : integer  := 2;
        C_DDR_DWIDTH            : integer  := 32;
        C_DDR_AWIDTH            : integer  := 13;
        C_DDR_COL_AWIDTH        : integer  := 9;
        C_DDR_BANK_AWIDTH       : integer  := 2;
        C_DDR_BRST_SIZE         : integer  := 8;
        C_IPIF_DWIDTH           : integer  := 64;
        C_IPIF_AWIDTH           : integer  := 32;
        C_INCLUDE_BURSTS        : integer  := 1;
        C_CLK_PERIOD            : integer  := 10000;
        C_OPB_BUS               : integer  := 0;
        C_PLB_BUS               : integer  := 1;
        -- simulation only generic (set to 200us)
        C_SIM_INIT_TIME_PS      : integer  := 200000000;
        C_INCLUDE_ECC_SUPPORT   : integer   := 0;
        NUM_ECC_BITS            : integer   := 7
     );  
  port (
        -- Test Bus
        ddr_test_cntl       : in   std_logic_vector(1 downto 0);
        ddr_test_bus        : out  std_logic_vector(19 downto 0);

    
        -- IPIC inputs
        Bus2IP_Addr         : in  std_logic_vector(0 to C_IPIF_AWIDTH-1);
        Bus2IP_BE           : in  std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
        Bus2IP_Data         : in  std_logic_vector(0 to C_IPIF_DWIDTH-1);
        Bus2IP_RNW          : in  std_logic;
        Bus2IP_RdReq        : in  std_logic;
        Bus2IP_WrReq        : in  std_logic;
        Bus2IP_Burst        : in  std_logic;
        Bus2IP_IBurst       : in  std_logic;
        Bus2IP_CS           : in  std_logic_vector(0 to C_NUM_BANKS_MEM-1);
        ECC_chk_bits_wr     : in  std_logic_vector (0 to NUM_ECC_BITS*2-1);
        ECC_chk_bits_rd     : out std_logic_vector (0 to NUM_ECC_BITS*2-1);

        -- IPIC outputs
        IP2Bus_Data         : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
        IP2Bus_WrAddrAck    : out std_logic;
        IP2Bus_RdAddrAck    : out std_logic;
        IP2Bus_Busy         : out std_logic;
        IP2Bus_RdAck        : out std_logic;
        IP2Bus_WrAck        : out std_logic;
        IP2Bus_ErrAck       : out std_logic;
        IP2Bus_Retry        : out std_logic;
        IP2Bus_ToutSup      : out std_logic;

        -- DDR interface signals
        DDR_Clk             : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1);
        DDR_Clkn            : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1);
        DDR_CKE             : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
        DDR_CSn             : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
        DDR_RASn            : out std_logic;
        DDR_CASn            : out std_logic;
        DDR_WEn             : out std_logic;
        DDR_DM              : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_BankAddr        : out std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
        DDR_Addr            : out std_logic_vector(0 to C_DDR_AWIDTH-1);
        DDR_DQ_o            : out std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DQ_i            : in  std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DQ_t            : out std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DQS_i           : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_DQS_o           : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_DQS_t           : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        
        -- DDR ECC interface signals
        DDR_DM_ECC          : out std_logic;
        DDR_DQ_ECC_o        : out std_logic_vector(0 to NUM_ECC_BITS-1);
        DDR_DQ_ECC_i        : in  std_logic_vector(0 to NUM_ECC_BITS-1);
        DDR_DQ_ECC_t        : out std_logic_vector(0 to NUM_ECC_BITS-1);
        DDR_DQS_ECC_i       : in  std_logic;
        DDR_DQS_ECC_o       : out std_logic;
        DDR_DQS_ECC_t       : out std_logic;

        -- Timer/Interrupt signals
        DDR_Init_done       : out std_logic;

        -- Clocks and reset
        Sys_Clk             : in  std_logic;
        Sys_Clk_n           : in  std_logic;
        Clk90_in            : in  std_logic;
        Clk90_in_n          : in  std_logic;
        DDR_Clk90_in        : in  std_logic;
        DDR_Clk90_in_n      : in  std_logic;
        Rst                 : in  std_logic
    );
end entity ddr_controller2;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

architecture imp of ddr_controller2 is

component io_registers2 is
  generic ( C_DDR_AWIDTH            : integer;
            C_DDR_BANK_AWIDTH       : integer;
            C_DDR_DWIDTH            : integer;
            C_IPIF_DWIDTH           : integer;
            C_INCLUDE_ECC_SUPPORT   : integer;
            NUM_ECC_BITS            : integer;
            C_FAMILY                : string := "virtex2";
            C_NUM_BANKS_MEM         : integer range 1 to 4 := 1
            );
  port (
        Write_data              : in  std_logic_vector(0 to C_IPIF_DWIDTH-1);
        Write_data_ecc          : in  std_logic_vector (0 to NUM_ECC_BITS*2-1);     -- ECC
        Write_data_en           : in  std_logic;
        Write_data_ecc_en       : in  std_logic;                                    -- ECC
        Write_dqs_en            : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        Write_dqs_ecc_en        : in  std_logic;                                    -- ECC

        Read_dqs_ce             : in  std_logic;
        Write_data_mask         : in  std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
        Write_data_ecc_mask     : in  std_logic_vector (0 to C_IPIF_DWIDTH/32-1);   -- ECC

        Read_data_en            : in  std_logic;
        DQ_oe_cmb               : in  std_logic;
        DQ_ECC_oe_cmb           : in  std_logic;                                    -- ECC
        DQS_oe                  : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DQS_ECC_oe              : in  std_logic;                                    -- ECC
        
        DQS_rst                 : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DQS_ECC_rst             : in  std_logic;                                    -- ECC
        DQS_setrst              : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DQS_ECC_setrst          : in  std_logic;                                    -- ECC
        CSn                     : in  std_logic_vector(0 to C_NUM_BANKS_MEM-1);
        RASn                    : in  std_logic;
        CASn                    : in  std_logic;
        WEn                     : in  std_logic;
        BankAddr                : in  std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
        Addr                    : in  std_logic_vector(0 to C_DDR_AWIDTH-1);
        DDR_ReadData            : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
        DDR_ReadData_ECC        : out std_logic_vector(0 to NUM_ECC_BITS*2-1);      -- ECC
        
        DDR_read_data_en        : out std_logic;
        DDR_DQ_i                : in  std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DQ_o                : out std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DQ_t                : out std_logic_vector(0 to C_DDR_DWIDTH-1);
        DDR_DM                  : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        
        DDR_DQ_ECC_i            : in    std_logic_vector(0 to NUM_ECC_BITS-1);      -- ECC
        DDR_DQ_ECC_o            : out   std_logic_vector(0 to NUM_ECC_BITS-1);      -- ECC
        DDR_DQ_ECC_t            : out   std_logic_vector(0 to NUM_ECC_BITS-1);      -- ECC
        DDR_DM_ECC              : out   std_logic;                                  -- ECC
        DDR_DQS_ECC_i           : in    std_logic;                                  -- ECC
        DDR_DQS_ECC_o           : out   std_logic;                                  -- ECC
        DDR_DQS_ECC_t           : out   std_logic;                                  -- ECC
        
        DDR_Read_DQS            : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_Read_DQS_ECC        : out std_logic;                                    -- ECC
        
        DDR_DQS_i               : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_DQS_o               : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_DQS_t               : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_CSn                 : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
        DDR_RASn                : out std_logic;       
        DDR_CASn                : out std_logic;
        DDR_WEn                 : out std_logic;
        DDR_BankAddr            : out std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
        DDR_Addr                : out std_logic_vector(0 to C_DDR_AWIDTH-1);
        Clk                     : in  std_logic;
        Clk_n                   : in  std_logic;
        Clk90                   : in  std_logic;
        Clk90_n                 : in  std_logic;
        Clk_ddr_rddata          : in  std_logic;
        Clk_ddr_rddata_n        : in  std_logic;
        Rst                     : in  std_logic
    );
end component;


component read_data_path2 is
  generic ( 
        C_IPIF_DWIDTH           : integer;
        C_DDR_DWIDTH            : integer;
        C_FAMILY                : string;
        C_INCLUDE_ECC_SUPPORT   : integer   := 0;
        NUM_ECC_BITS            : integer
        );
  port (
        ddr_test_cntl           : in  std_logic_vector(1 downto 0);
        ddr_rd_bus              : out  std_logic_vector(19 downto 0);
        DDR_ReadData            : in  std_logic_vector(0 to C_IPIF_DWIDTH-1);
        DDR_ReadData_ECC        : in  std_logic_vector(0 to NUM_ECC_BITS*2-1);      -- ECC
        DDR_ReadDQS             : in  std_logic_vector(0 to C_DDR_DWIDTH/8-1);
        DDR_ReadDQS_ECC         : in  std_logic;                                    -- ECC
        DDR_read_data_en        : in  std_logic;
        Read_data_en            : in  std_logic;
        RdAck_rst               : in  std_logic;
        Read_data               : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
        ECC_chk_bits_rd         : out std_logic_vector(0 to NUM_ECC_BITS*2-1);      -- ECC
        RdAck                   : out std_logic;

        -- Clocks and reset
        Clk                     : in  std_logic;
        Clk_ddr_rddata          : in  std_logic;
        Rst                     : in  std_logic
    );
end component;

-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
type INTEGER_ARRAY is array (natural range <>) of integer;
-- function max returns the max value of an array