📄 ipic_if.vhd
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-------------------------------------------------------------------------------
-- $Id: ipic_if.vhd,v 1.1 2004/04/06 23:13:04 jennj Exp $
-------------------------------------------------------------------------------
-- ipic_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipic_if.vhd
-- Version: v1.10a
-- Description: This file interfaces to the IPIC and sets signals for the
-- command state machine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/14/02 First Version
--
-- ALS 06/4/02
-- ^^^^^^
-- Fixed address bus assignments based on DDR data widths
-- ~~~~~~
-- ALS 06/06/02
-- ^^^^^^
-- Added reset of pendrdreq and pendwrreq when CS negates. Qualified read_op
-- and write_op with RNW.
-- ~~~~~~
-- ALS 06/11/02
-- ^^^^^^
-- Added assertion of RETRY while CS=1 and INIT_DONE=0.
-- ~~~~~~
-- ALS 06/26/03
-- ^^^^^^
-- Added IP2Bus_Busy which gets asserted during initialization. No longer
-- assert ErrAck during initialization. Added IP2Bus_AddrAck. Assert ToutSup
-- for all transactions.
-- ~~~~~~
-- ALS 07/08/03
-- ^^^^^^
-- Removed all unused signals and ports.
-- ~~~~~~
-- ALS 07/15/03
-- ^^^^^^
-- Changed ToutSup from being asserted anytime Bus2IP_CS asserts to being asserted
-- in most states except in PRECHARGE when waiting for read_data_done. This is
-- to insure that if read_data_done doesn't assert for some reason, the bus will
-- not be hung and an error will be generated.
-- ~~~~~~
-- JLJ 11/11/03
-- ^^^^^^
-- Version D: Add ECC check bits to I/O port. Seperate IP2Bus_AddrAck into
-- IP2Bus_WrAddrAck and IP2Bus_RdAddrAck.
-- ~~~~~~
-- JLJ 02/20/04
-- ^^^^^^
-- Add support for multiple memory banks. Utilize C_NUM_BANKS_MEM parameter to
-- size Bus2IP_CS signal. Added Comb_Bus2IP_CS as output signal.
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- number of memory banks
-- C_DDR_AWIDTH -- DDR address width
-- C_DDR_DWIDTH -- DDR data width
-- C_DDR_COL_AWIDTH -- DDR column address width
-- C_DDR_BANK_AWIDTH -- DDR bank address width
-- C_IPIF_DWIDTH -- IPIF data width
-- C_IPIF_AWIDTH -- IPIF address width
-- C_INCLUDE_BURSTS -- support bus burst transactions
-- NUM_ECC_BITS -- number of ECC check bits
--
-- Definition of Ports:
-- Bus2IP_CS -- indicates DDR SDRAM controller has been selected
-- Bus2IP_Addr -- address
-- Bus2IP_Burst -- burst
-- Bus2IP_Data -- processor bus data
-- ECC_chk_bits_wr_in -- ECC check bit bus data
-- Bus2IP_BE -- byte enables
-- Bus2IP_RdReq -- read req
-- Bus2IP_WrReq -- write req
-- IP2Bus_ErrAck -- error acknowledge
-- IP2Bus_Retry -- retry
-- IP2Bus_Busy -- IP is busy, re-arbitrate transactions
-- IP2Bus_AddrAck -- IP address acknowledge
-- IP2Bus_WrAck -- write acknowledge
-- IP2Bus_RdAck -- read acknowledge
-- IP2Bus_ToutSup -- suppress timeout counter
-- IP2Bus_data -- read data from DDR
-- ECC_chk_bits_rd_out -- ECC read data from DDR
-- WrAck -- write acknowledge
-- RdAck -- read acknowledge
-- ToutSup -- timeout suppress
-- Read_data -- data read from DDR
-- ECC_chk_bits_rd_in -- ECC data read from DDR
-- Retry -- retry transaction
-- Init_done -- initialization is complete
-- Comb_Bus2IP_CS -- combined Bus2IP_CS signal
-- IPIC_wrdata -- data to be written to DDR
-- ECC_chk_bits_wr_out -- ECC data to be written to DDR
-- IPIC_be -- byte enables from bus
-- Burst -- bus burst transaction
-- Reset_pendrdreq -- reset pending read request
-- Reset_pendwrreq -- reset pending write request
-- Row_addr -- row address
-- Col_addr -- column address
-- Bank_addr -- bank address
-- Pend_rdreq -- pending read request
-- Pend_wrreq -- pending write request
-- Same_row -- pending transaction is for the same row
-- Same_bank -- pending transaction is for the same bank
--
-- -- Clocks and reset
-- Clk
-- Rst
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity ipic_if is
generic (
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_DDR_AWIDTH : integer;
C_DDR_DWIDTH : integer;
C_DDR_COL_AWIDTH : integer;
C_DDR_BANK_AWIDTH : integer;
C_IPIF_AWIDTH : integer;
C_IPIF_DWIDTH : integer;
C_INCLUDE_BURSTS : integer;
C_INCLUDE_ECC_SUPPORT : integer;
NUM_ECC_BITS : integer
);
port (
Bus2IP_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_Burst : in std_logic;
Bus2IP_IBurst : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_wr_in : in std_logic_vector(0 to NUM_ECC_BITS*2-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_ErrAck : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Busy : out std_logic;
IP2Bus_WrAddrAck : out std_logic;
IP2Bus_RdAddrAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_rd_out : out std_logic_vector(0 to NUM_ECC_BITS*2-1);
Wr_AddrAck : in std_logic;
Rd_AddrAck : in std_logic;
WrAck : in std_logic;
RdAck : in std_logic;
ToutSup : in std_logic;
Read_data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_rd_in : in std_logic_vector(0 to NUM_ECC_BITS*2-1);
Retry : in std_logic;
Init_done : in std_logic;
Comb_Bus2IP_CS : out std_logic;
IPIC_wrdata : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
ECC_chk_bits_wr_out : out std_logic_vector(0 to NUM_ECC_BITS*2-1);
IPIC_be : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Burst : out std_logic;
Reset_pendrdreq : in std_logic;
Reset_pendwrreq : in std_logic;
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