ddr_ctrl.cr.mti

xilinx ddr3最新VHDL代码,通过调试

** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/ddr_controller2.vhd(189): Unknown identifier 'ddr_v1_10_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/ddr_controller2.vhd(288): VHDL Compiler exiting

} {7.0 8.0 9.0 13.0 14.0 17.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd(94): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd(95): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd(96): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/init_statemachine.vhd(132): VHDL Compiler exiting

} {7.0 8.0 9.0 13.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(143): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(144): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(145): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(146): Unknown identifier 'proc_common_v2_00_a'.
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(148): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(149): Unknown identifier 'unisim'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers2.vhd(228): VHDL Compiler exiting

} {7.0 8.0 9.0 14.0 15.0 18.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(130): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(131): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(132): Unknown identifier 'proc_common_v2_00_a'.
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(134): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(135): Unknown identifier 'unisim'.
** Error: (vcom-19) Failed to access library 'xilinxcorelib' at "xilinxcorelib".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(138): Library xilinxcorelib not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/read_data_path2.vhd(174): VHDL Compiler exiting

} {7.0 8.0 9.0 13.0 14.0 17.0 18.0 20.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package attributes
-- Loading package std_logic_misc
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(194): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(195): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(196): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(197): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(198): Unknown identifier 'proc_common_v2_00_a'.
** Error: (vcom-19) Failed to access library 'ddr_v1_10_a' at "ddr_v1_10_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(200): Library ddr_v1_10_a not found.
** Error: (vcom-19) Failed to access library 'opb_ipif_v3_01_b' at "opb_ipif_v3_01_b".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(203): Library opb_ipif_v3_01_b not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(204): Unknown identifier 'opb_ipif_v3_01_b'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/cntl_ddr2.vhd(300): VHDL Compiler exiting

} {9.0 10.0 11.0 17.0 18.0 20.0 21.0 24.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(181): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(182): Unknown identifier 'unisim'.
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(184): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(185): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(186): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/command_statemachine.vhd(294): VHDL Compiler exiting

} {7.0 8.0 9.0 12.0 13.0 17.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(139): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(140): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(141): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(142): Unknown identifier 'proc_common_v2_00_a'.
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(144): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(145): Unknown identifier 'unisim'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/clock_gen.vhd(177): VHDL Compiler exiting

} {7.0 8.0 9.0 14.0 15.0 18.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(145): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(146): Unknown identifier 'unisim'.
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(148): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(149): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(150): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/data_statemachine.vhd(204): VHDL Compiler exiting

} {7.0 8.0 9.0 12.0 13.0 17.0} {}} E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd {0 {vcom -work ddr_ctrl -2002 -explicit E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd
Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
** Error: (vcom-19) Failed to access library 'proc_common_v2_00_a' at "proc_common_v2_00_a".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(143): Library proc_common_v2_00_a not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(144): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(145): Unknown identifier 'proc_common_v2_00_a'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(146): Unknown identifier 'proc_common_v2_00_a'.
** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
No such file or directory. (errno = ENOENT)
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(148): Library unisim not found.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(149): Unknown identifier 'unisim'.
** Error: E:/work/altera/cntl_ddr3/cntl_ddr3/io_registers.vhd(228): VHDL Compiler exiting

} {7.0 8.0 9.0 14.0 15.0 18.0} {}}