📄 io_registers.vhd
字号:
-------------------------------------------------------------------------------
-- $Id: io_registers.vhd,v 1.6 2004/11/19 23:00:32 linnj Exp $
-------------------------------------------------------------------------------
-- io_registers.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: io_registers.vhd
-- Version: v1.10a
-- Description: This file contains all of the io_registers for the DDR design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- init_statemachine.vhd
-- -- clock_gen.vhd
-- -- counters.vhd
-- -- command_statemachine.vhd
-- -- data_statemachine.vhd
-- -- io_registers.vhd
-- -- read_data_path.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/13/02 First Version
--
-- ALS 06/04/02
-- ^^^^^^
-- Added XON generic and set to false for zero-delay simulations
-- ~~~~~~
-- ALS 06/07/02
-- ^^^^^^
-- Added input register for DQS which is asynchronously held in reset by
-- read_data_en.
-- ~~~~~~
-- ALS 06/11/02
-- ^^^^^^
-- Changed reset of DQS input register because there is only one reset in IOB.
-- Instead, synchronized read_data_en and used it as clock enable. Used
-- Clk90 for DQST so it can go into IOB with DQS.
-- ~~~~~~
-- ALS 09/25/02
-- ^^^^^^
-- To allow for either pullups or pulldowns on DQS, will now register DQS on
-- both falling and rising edge of DDR clock and verify that it is 0 and then 1
-- before writing data to the FIFO. Will output the DDR_READ_DATA_ENABLE signal
-- to the read data path module to qualify the FIFO write enable signal.
-- ~~~~~~
-- ALS 06/25/03
-- ^^^^^^
-- Removed XON generic from unisim component instantiations.
-- ~~~~~~
-- JLJ 11/11/03
-- ^^^^^^
-- Version D: Update to include ECC register logic.
-- ~~~~~~
-- JLJ 02/16/04
-- ^^^^^^
-- Removed C_PULLUPS generic. If this parameter was set to 1, the DDR DQS lines
-- had pullups. If this parameter was set to 0, then pulldowns were assumed. The
-- new default setting will assume pullups.
-- ~~~~~~
-- JLJ 02/18/04
-- ^^^^^^
-- Added the following inputs: Clk_n, Clk90_n, & Clk_ddr_rddata_n
-- This update requires global inversion on clock inputs to prevent any
-- duty cycle distortion as system frequencies increase.
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a. Added C_FAMILY
-- parameter to determine type of I/O DDR registers instantiated.
-- ~~~~~~
-- JLJ 05/05/04
-- ^^^^^^
-- Add component declaration for Virtex-4 primitives: IDDR & ODDR.
-- ~~~~~~
-- JLJ 08/09/04
-- ^^^^^^
-- Remove component declaration for Virtex-4 primitives: IDDR & ODDR.
-- ~~~~~~
-- JLJ 10/19/04
-- ^^^^^^
-- Remove IOB TRUE attribute on DDR_DQS signal for Virtex-4.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.family.all;
use proc_common_v2_00_a.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DDR_AWIDTH -- width of DDR address bus
-- C_DDR_BANK_AWIDTH -- width of DDR bank address bus
-- C_DDR_DWIDTH -- length of DDR burst
-- C_IPIF_DWIDTH -- DDR CAS latency
-- C_FAMILY -- target FPGA family type
-- NUM_ECC_BITS -- number of ECC check bits
--
-- Definition of Ports:
-- -- inputs
-- Write_data -- data to be written to DDR
-- Write_data_ecc -- ECC data to be written to DDR
-- Write_data_en -- write data enable
-- Write_data_ecc_en -- ECC write data enable
-- Write_dqs_en -- write dqs enable
-- Write_dqs_ecc_en -- ECC write dqs enable
-- Read_dqs_ce -- read dqs clock enable
-- Write_data_mask -- data mask to DDR
-- Write_data_ecc_mask -- ECC data mask to DDR
-- Read_data_en -- read data clock enable
-- DQ_oe_cmb -- combinational DQ output enable
-- DQ_ECC_oe_cmb -- ECC combinational DQ output enable
-- DQS_oe -- DQS output enable
-- DQS_ECC_oe -- ECC DQS output enable
-- DQS_rst -- DQS reset
-- DQS_ECC_rst -- ECC DQS reset
-- DQS_setrst -- DQS set/reset
-- DQS_ECC_setrst -- ECC DQS set/reset
-- CSn -- CSn for DDR
-- RASn -- RASn for DDR
-- CASn -- CASn for DDR
-- WEn -- WEn for DDR
-- BankAddr -- bank address for DDR
-- Addr -- address for DDR
-- DDR_DQ_i -- input data from DDR
-- DDR_DQS_i -- input DQS from DDR
-- DDR_DQ_ECC_i -- input ECC data from DDR
-- DDR_DQS_ECC_i -- input ECC DQS from DDR
--
-- -- outputs
-- DDR_DQ_o -- DQ output to DDR
-- DDR_DQ_t -- DQ output enable
-- DDR_DM -- DDR data mask
-- DDR_DQ_ECC_o -- ECC DQ output to DDR
-- DDR_DQ_ECC_t -- ECC DQ output enable
-- DDR_DM_ECC -- ECC DDR data mask
-- DDR_Read_DQS -- DQS value read from DDR
-- DDR_Read_DQS_ECC -- ECC DQS value read from DDR
-- DDR_DQS_o -- DQS output to DDR
-- DDR_DQS_t -- DQS output enable
-- DDR_DQS_ECC_o -- ECC DQS output to DDR
-- DDR_DQS_ECC_t -- ECC DQS output enable
-- DDR_CSn -- CSn output to DDR
-- DDR_RASn -- RASn output to DDR
-- DDR_CASn -- CASn output to DDR
-- DDR_WEn -- WEn output to DDR
-- DDR_BankAddr -- bank address output to DDR
-- DDR_Addr -- address output to DDR
-- DDR_ReadData -- data readback from DDR
-- DDR_ReadData_ECC -- ECC data readback from DDR
-- DDR_read_data_en -- data readback enable from DDR
--
-- -- Clocks and reset
-- Clk -- bus clock
-- Clk_n -- bus clock phase shifted by 180 degrees
-- Clk90 -- bus clock phase shifted by 90 degrees
-- Clk90_n -- bus clock phase shifted by 270 degrees
-- Clk_ddr_rddata -- DDR feedback clock shifted 90
-- Clk_ddr_rddata_n -- DDR feedback clock shifted 270
-- Rst
---------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity io_registers is
generic ( C_DDR_AWIDTH : integer;
C_DDR_BANK_AWIDTH : integer;
C_DDR_DWIDTH : integer;
C_IPIF_DWIDTH : integer;
C_INCLUDE_ECC_SUPPORT : integer;
NUM_ECC_BITS : integer;
C_FAMILY : string := "virtex2";
C_NUM_BANKS_MEM : integer range 1 to 4 := 1
);
port (
Write_data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Write_data_ecc : in std_logic_vector (0 to NUM_ECC_BITS*2-1); -- ECC
Write_data_en : in std_logic;
Write_data_ecc_en : in std_logic; -- ECC
Write_dqs_en : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
Write_dqs_ecc_en : in std_logic; -- ECC
Read_dqs_ce : in std_logic;
Write_data_mask : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Write_data_ecc_mask : in std_logic_vector (0 to C_IPIF_DWIDTH/32-1); -- ECC
Read_data_en : in std_logic;
DQ_oe_cmb : in std_logic;
DQ_ECC_oe_cmb : in std_logic; -- ECC
DQS_oe : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DQS_ECC_oe : in std_logic; -- ECC
DQS_rst : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DQS_ECC_rst : in std_logic; -- ECC
DQS_setrst : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DQS_ECC_setrst : in std_logic; -- ECC
CSn : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
BankAddr : in std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
Addr : in std_logic_vector(0 to C_DDR_AWIDTH-1);
DDR_ReadData : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
DDR_ReadData_ECC : out std_logic_vector(0 to NUM_ECC_BITS*2-1); -- ECC
DDR_read_data_en : out std_logic;
DDR_DQ_i : in std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DQ_o : out std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DQ_t : out std_logic_vector(0 to C_DDR_DWIDTH-1);
DDR_DM : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_DQ_ECC_i : in std_logic_vector(0 to NUM_ECC_BITS-1); -- ECC
DDR_DQ_ECC_o : out std_logic_vector(0 to NUM_ECC_BITS-1); -- ECC
DDR_DQ_ECC_t : out std_logic_vector(0 to NUM_ECC_BITS-1); -- ECC
DDR_DM_ECC : out std_logic; -- ECC
DDR_DQS_ECC_i : in std_logic; -- ECC
DDR_DQS_ECC_o : out std_logic; -- ECC
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -