📄 counters.vhd
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RST => Rst,
Q => gp_cnt,
LD => GPcnt_data,
AD => "1",
LOAD => gpcnt_load_delay,
OP => gpcnt_en_delay
);
-- RC delay counter
trc_cnt_en <= not(Trc_load);
RCCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_RCCNT_WIDTH,
C_RESET_VALUE => RCCNT_RST,
C_LD_WIDTH => C_RCCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => rc_cnt,
LD => C_RCCNT,
AD => "1",
LOAD => Trc_load,
OP => trc_cnt_en
);
-- RRD delay counter
trrd_cnt_en <= not(Trrd_load);
RRDCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_RRDCNT_WIDTH,
C_RESET_VALUE => RRDCNT_RST,
C_LD_WIDTH => C_RRDCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => rrd_cnt,
LD => C_RRDCNT,
AD => "1",
LOAD => Trrd_load,
OP => trrd_cnt_en
);
-- RAS delay counter
tras_cnt_en <= not(Tras_load);
RASCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_RASCNT_WIDTH,
C_RESET_VALUE => RASCNT_RST,
C_LD_WIDTH => C_RASCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => ras_cnt,
LD => C_RASCNT,
AD => "1",
LOAD => Tras_load,
OP => tras_cnt_en
);
-- Refresh and powerup delay counter
refi_pwrup_load <= Tpwrup_load or Trefi_load;
refi_pwrup_cnten <= not(refi_pwrup_load);
refi_pwrup_data <= C_200CK_CNT when Tpwrup_load = '1'
else C_REFICNT;
REFI_PWRUP_CNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_REFICNT_WIDTH,
C_RESET_VALUE => C_200US_CNT,
C_LD_WIDTH => C_REFICNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => refi_pwrup_cnt,
LD => refi_pwrup_data,
AD => "1",
LOAD => refi_pwrup_load,
OP => refi_pwrup_cnten
);
-- WR delay counter
-- counter is only needed if C_WRCNT > 0
WRCNT_GEN: if C_WRCNT > 0 generate
twr_cnt_en <= not(twr_load) and Twr_cnten after 1 ns;
twr_rst_i <= Twr_rst after 1 ns;
WRCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_WRCNT_WIDTH,
C_RESET_VALUE => WRCNT_RST,
C_LD_WIDTH => C_WRCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => twr_rst_i,
Q => wr_cnt,
LD => C_WRCNT,
AD => "1",
LOAD => Twr_load,
OP => twr_cnt_en
);
WRCNT_END_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
Twr_end <= '0';
elsif Twr_rst = '1' then
Twr_end <= '0';
elsif wr_cnt = WRCNT_END then
Twr_end <= '1';
end if;
end if;
end process WRCNT_END_PROCESS;
end generate WRCNT_GEN;
NOWRCNT_GEN: if C_WRCNT = 0 generate
WRCNT_END_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
Twr_end <= '0';
elsif Twr_load = '1' then
Twr_end <= '1';
elsif Twr_rst = '1' then
Twr_end <= '0';
end if;
end if;
end process WRCNT_END_PROCESS;
end generate NOWRCNT_GEN;
CASLAT_GT_2_GEN: if C_CASLAT > 2 generate
constant CASLAT_MINUS_ONE_END :std_logic_vector(0 to C_CASLATCNT_WIDTH-1):=
conv_std_logic_vector(2,C_CASLATCNT_WIDTH);
begin
CASLATCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_CASLATCNT_WIDTH,
C_RESET_VALUE => CASLATCNT_RST,
C_LD_WIDTH => C_CASLATCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => caslat_cnt,
LD => C_CASLATCNT,
AD => "1",
LOAD => tcaslat_load,
OP => tcaslat_cnt_en
);
CASLAT_MINUS1_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
tcaslat_minus1_i <= '0';
Tcaslat_end <= '0';
else
Tcaslat_end <= tcaslat_minus1_i;
if caslat_cnt = CASLAT_MINUS_ONE_END and Tcaslat_cnt_en = '1' then
tcaslat_minus1_i <= '1';
else
tcaslat_minus1_i <= '0';
end if;
end if;
end if;
end process CASLAT_MINUS1_PROCESS;
end generate CASLAT_GT_2_GEN;
CASLAT_EQ_2_GEN: if C_CASLAT <= 2 generate
CASLAT_MINUS1_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
tcaslat_minus1_i <= '0';
Tcaslat_end <= '0';
else
tcaslat_minus1_i <= Tcaslat_load;
Tcaslat_end <= tcaslat_minus1_i;
end if;
end if;
end process CASLAT_MINUS1_PROCESS;
end generate CASLAT_EQ_2_GEN;
-------------------------------------------------------------------------------
-- Generate the counter end signals
-- Generate signal when counter is at '1' so that the end signal can be
-- registered
-------------------------------------------------------------------------------
CNTR_END_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
GPcnt_end <= '0';
Trc_end <= '0';
Trrd_end <= '0';
Tras_end <= '0';
Trefi_pwrup_end <= '0';
else
-- if GPcnt_data = ZERO_GPCNT or GPcnt_data=GPCNTR_END then
if GPcnt_data = ZERO_GPCNT then
GPcnt_end <= gpcnt_load_delay;
elsif gpcnt_load_delay='1' then
GPcnt_end <= '0';
elsif gp_cnt = GPCNTR_END then
GPcnt_end <= '1';
end if;
-- The Trc_end, Trrd_end, and Tras_end signals must
-- stay asserted until the counters are reloaded.
if Trc_load = '1' then
Trc_end <= '0';
elsif rc_cnt = RCCNT_END then
Trc_end <= '1';
end if;
if Trrd_load = '1' then
Trrd_end <= '0';
elsif rrd_cnt = RRDCNT_END then
Trrd_end <= '1';
end if;
if Tras_load = '1' then
Tras_end <= '0';
elsif ras_cnt = RASCNT_END then
Tras_end <= '1';
end if;
-- the refresh timer interval end signal must
-- stay asserted until the refresh can be serviced
-- reset it once the load signal occurs again
if refi_pwrup_load = '1' then
Trefi_pwrup_end <= '0';
elsif refi_pwrup_cnt = REFICNT_END then
Trefi_pwrup_end <= '1';
elsif Init_done = '0' then
Trefi_pwrup_end <= '0';
end if;
end if;
end if;
end process CNTR_END_PROCESS;
BRSTCNT_EQ2_GEN: if C_DDR_BRST_SIZE <= 2 generate
brst_cnt <= (others => '0');
cmd_cnt <= (others => '0');
DDR_BRST2_END_PROCESS: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
ddr_brst_end_i <= '0';
Tcmd_end <= '0';
else
ddr_brst_end_i <= Tbrst_load;
Tcmd_end <= Tcmd_load after 1 nS;
end if;
end if;
end process DDR_BRST2_END_PROCESS;
end generate BRSTCNT_EQ2_GEN;
BRSTCNT_GT_2_GEN: if C_DDR_BRST_SIZE > 2 generate
-- BrstLen div 2 delay counter
BRSTLEN2_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_BRSTCNT_WIDTH,
C_RESET_VALUE => BRSTCNT_RST,
C_LD_WIDTH => C_BRSTCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => brst_cnt,
LD => C_BRSTCNT,
AD => "1",
LOAD => Tbrst_load,
OP => Tbrst_cnt_en
);
-- Command delay counter
CMDCNT_I: ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_BRSTCNT_WIDTH,
C_RESET_VALUE => CMDCNT_RST,
C_LD_WIDTH => C_BRSTCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => cmd_cnt,
LD => C_CMDCNT,
AD => "1",
LOAD => Tcmd_load,
OP => Tcmd_cnt_en
);
DDR_BRST_END_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
ddr_brst_end_i <= '0';
Tcmd_end <= '0';
else
if cmd_cnt = CMDCNT_END and Tcmd_cnt_en = '1' then
Tcmd_end <= '1' after 1 ns;
else
Tcmd_end <= '0'after 1 ns;
end if;
if brst_cnt = BRSTCNT_END and Tbrst_cnt_en = '1' then
ddr_brst_end_i <= '1';
else
ddr_brst_end_i <= '0';
end if;
end if;
end if;
end process DDR_BRST_END_PROCESS;
end generate BRSTCNT_GT_2_GEN;
end imp;⌨️ 快捷键说明
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