decoder.vhd

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(d:in std_logic_vector(3 downto 0);
     q:out std_logic_vector(6 downto 0));
end;
architecture de of decoder is
begin 
process(d)
begin 
case d is
when"0000"=>q<="1111110";
when"0001"=>q<="0110000";
when"0010"=>q<="1101101";
when"0011"=>q<="1111001";
when"0100"=>q<="0110011";
when"0101"=>q<="1011011";
when"0110"=>q<="1011111";
when"0111"=>q<="1110000";
when"1000"=>q<="1111111";
when"1001"=>q<="1111011";
when others=>null;
end case;
end process;
end;