fre_20.vhd

来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fre_20 is
  port(clk:in std_logic;
       q:buffer std_logic);
end;
architecture fre of fre_20 is 
signal a:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then 
   if a>="1001" then
    q<=not q;
    a<="0000";
   else a<=a+'1';
   end if;
end if;
end process;
end;