timer.hier_info

来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· HIER_INFO 代码 · 共 359 行

|timer
q[0] <= DECODER:2.q[0]
q[1] <= DECODER:2.q[1]
q[2] <= DECODER:2.q[2]
q[3] <= DECODER:2.q[3]
q[4] <= DECODER:2.q[4]
q[5] <= DECODER:2.q[5]
q[6] <= DECODER:2.q[6]
clk => FRE_100:8.clk
clr => D_FF:18.d0
pause => D_FF:18.d1
sel => D_FF:18.d2
set => D_FF:18.d3
sel7 <= DECODER_DYNAMIC:13.sel[7]
sel6 <= DECODER_DYNAMIC:13.sel[6]
sel5 <= DECODER_DYNAMIC:13.sel[5]
sel4 <= DECODER_DYNAMIC:13.sel[4]
sel3 <= DECODER_DYNAMIC:13.sel[3]
sel2 <= DECODER_DYNAMIC:13.sel[2]
sel1 <= DECODER_DYNAMIC:13.sel[1]
sel0 <= DECODER_DYNAMIC:13.sel[0]


|timer|decoder:2
d[0] => Mux0.IN19
d[0] => Mux1.IN19
d[0] => Mux2.IN19
d[0] => Mux3.IN19
d[0] => Mux4.IN19
d[0] => Mux5.IN19
d[0] => Mux6.IN19
d[0] => Mux7.IN19
d[1] => Mux0.IN18
d[1] => Mux1.IN18
d[1] => Mux2.IN18
d[1] => Mux3.IN18
d[1] => Mux4.IN18
d[1] => Mux5.IN18
d[1] => Mux6.IN18
d[1] => Mux7.IN18
d[2] => Mux0.IN17
d[2] => Mux1.IN17
d[2] => Mux2.IN17
d[2] => Mux3.IN17
d[2] => Mux4.IN17
d[2] => Mux5.IN17
d[2] => Mux6.IN17
d[2] => Mux7.IN17
d[3] => Mux0.IN16
d[3] => Mux1.IN16
d[3] => Mux2.IN16
d[3] => Mux3.IN16
d[3] => Mux4.IN16
d[3] => Mux5.IN16
d[3] => Mux6.IN16
d[3] => Mux7.IN16
q[0] <= q[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]$latch.DB_MAX_OUTPUT_PORT_TYPE


|timer|decoder_dynamic:13
clk => temp[0].CLK
clk => temp[1].CLK
clk => temp[2].CLK
h1[0] => Mux3.IN0
h1[1] => Mux2.IN0
h1[2] => Mux1.IN0
h1[3] => Mux0.IN0
h0[0] => Mux3.IN1
h0[1] => Mux2.IN1
h0[2] => Mux1.IN1
h0[3] => Mux0.IN1
m1[0] => Mux3.IN2
m1[1] => Mux2.IN2
m1[2] => Mux1.IN2
m1[3] => Mux0.IN2
m0[0] => Mux3.IN3
m0[1] => Mux2.IN3
m0[2] => Mux1.IN3
m0[3] => Mux0.IN3
s0[0] => Mux3.IN4
s0[1] => Mux2.IN4
s0[2] => Mux1.IN4
s0[3] => Mux0.IN4
s1[0] => Mux3.IN5
s1[1] => Mux2.IN5
s1[2] => Mux1.IN5
s1[3] => Mux0.IN5
x0[0] => Mux3.IN6
x0[1] => Mux2.IN6
x0[2] => Mux1.IN6
x0[3] => Mux0.IN6
x1[0] => Mux3.IN7
x1[1] => Mux2.IN7
x1[2] => Mux1.IN7
x1[3] => Mux0.IN7
q[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
sel[3] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
sel[4] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
sel[5] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
sel[6] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
sel[7] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE


|timer|fre_100:4
clk => a[0].CLK
clk => a[1].CLK
clk => a[2].CLK
clk => a[3].CLK
clk => a[4].CLK
clk => a[5].CLK
clk => q~reg0.CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|fre_100:8
clk => a[0].CLK
clk => a[1].CLK
clk => a[2].CLK
clk => a[3].CLK
clk => a[4].CLK
clk => a[5].CLK
clk => q~reg0.CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|hour:17
clk => co~reg0.CLK
clk => shi[0]~reg0.CLK
clk => shi[1]~reg0.CLK
clk => shi[2]~reg0.CLK
clk => shi[3]~reg0.CLK
clk => ge[0]~reg0.CLK
clk => ge[1]~reg0.CLK
clk => ge[2]~reg0.CLK
clk => ge[3]~reg0.CLK
clr => co~reg0.ACLR
clr => shi[0]~reg0.ACLR
clr => shi[1]~reg0.ACLR
clr => shi[2]~reg0.ACLR
clr => shi[3]~reg0.ACLR
clr => ge[0]~reg0.ACLR
clr => ge[1]~reg0.ACLR
clr => ge[2]~reg0.ACLR
clr => ge[3]~reg0.ACLR
set1 => shi~20.OUTPUTSELECT
set1 => shi~21.OUTPUTSELECT
set1 => shi~22.OUTPUTSELECT
set1 => shi~23.OUTPUTSELECT
set1 => ge[0]~reg0.ENA
set1 => ge[1]~reg0.ENA
set1 => ge[2]~reg0.ENA
set1 => ge[3]~reg0.ENA
set0 => shi~16.OUTPUTSELECT
set0 => shi~17.OUTPUTSELECT
set0 => shi~18.OUTPUTSELECT
set0 => shi~19.OUTPUTSELECT
set0 => ge~12.OUTPUTSELECT
set0 => ge~13.OUTPUTSELECT
set0 => ge~14.OUTPUTSELECT
set0 => ge~15.OUTPUTSELECT
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[0] <= ge[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[1] <= ge[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[2] <= ge[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[3] <= ge[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[0] <= shi[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[1] <= shi[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[2] <= shi[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[3] <= shi[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|contr:26
clk => Mux7.IN7
clk1 => Mux9.IN5
clk2 => Mux11.IN5
clk3 => Mux13.IN5
pause => comb~0.IN0
pause => comb~1.IN0
pause => comb~2.IN0
pause => comb~3.IN0
pause => comb~5.IN0
sel => tem[0].CLK
sel => tem[1].CLK
sel => tem[2].CLK
set => Mux9.IN6
set => Mux9.IN7
set => Mux11.IN6
set => Mux11.IN7
set => Mux13.IN6
set => Mux13.IN7
clkh <= clkh$latch.DB_MAX_OUTPUT_PORT_TYPE
clkm <= clkm$latch.DB_MAX_OUTPUT_PORT_TYPE
clks <= clks$latch.DB_MAX_OUTPUT_PORT_TYPE
clkmm <= clkmm$latch.DB_MAX_OUTPUT_PORT_TYPE
s0 <= s0$latch.DB_MAX_OUTPUT_PORT_TYPE
s1 <= s1$latch.DB_MAX_OUTPUT_PORT_TYPE
s2 <= s2$latch.DB_MAX_OUTPUT_PORT_TYPE
s3 <= s3$latch.DB_MAX_OUTPUT_PORT_TYPE
s4 <= s4$latch.DB_MAX_OUTPUT_PORT_TYPE
s5 <= s5$latch.DB_MAX_OUTPUT_PORT_TYPE


|timer|fre_20:5
clk => a[0].CLK
clk => a[1].CLK
clk => a[2].CLK
clk => a[3].CLK
clk => q~reg0.CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|mms:6
clk => co~reg0.CLK
clk => shi[0]~reg0.CLK
clk => shi[1]~reg0.CLK
clk => shi[2]~reg0.CLK
clk => shi[3]~reg0.CLK
clk => ge[0]~reg0.CLK
clk => ge[1]~reg0.CLK
clk => ge[2]~reg0.CLK
clk => ge[3]~reg0.CLK
clr => shi[0]~reg0.ACLR
clr => shi[1]~reg0.ACLR
clr => shi[2]~reg0.ACLR
clr => shi[3]~reg0.ACLR
clr => ge[0]~reg0.ACLR
clr => ge[1]~reg0.ACLR
clr => ge[2]~reg0.ACLR
clr => ge[3]~reg0.ACLR
clr => co~reg0.ENA
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[0] <= ge[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[1] <= ge[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[2] <= ge[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[3] <= ge[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[0] <= shi[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[1] <= shi[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[2] <= shi[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[3] <= shi[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|d_ff:18
clk => q3~reg0.CLK
clk => q2~reg0.CLK
clk => q1~reg0.CLK
clk => q0~reg0.CLK
d0 => q0~reg0.DATAIN
d1 => q1~reg0.DATAIN
d2 => q2~reg0.DATAIN
d3 => q3~reg0.DATAIN
q0 <= q0~reg0.DB_MAX_OUTPUT_PORT_TYPE
q1 <= q1~reg0.DB_MAX_OUTPUT_PORT_TYPE
q2 <= q2~reg0.DB_MAX_OUTPUT_PORT_TYPE
q3 <= q3~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|sec:10
clk => co~reg0.CLK
clk => shi[0]~reg0.CLK
clk => shi[1]~reg0.CLK
clk => shi[2]~reg0.CLK
clk => shi[3]~reg0.CLK
clk => ge[0]~reg0.CLK
clk => ge[1]~reg0.CLK
clk => ge[2]~reg0.CLK
clk => ge[3]~reg0.CLK
clr => shi[0]~reg0.ACLR
clr => shi[1]~reg0.ACLR
clr => shi[2]~reg0.ACLR
clr => shi[3]~reg0.ACLR
clr => ge[0]~reg0.ACLR
clr => ge[1]~reg0.ACLR
clr => ge[2]~reg0.ACLR
clr => ge[3]~reg0.ACLR
set0 => shi~16.OUTPUTSELECT
set0 => shi~17.OUTPUTSELECT
set0 => shi~18.OUTPUTSELECT
set0 => shi~19.OUTPUTSELECT
set0 => ge~12.OUTPUTSELECT
set0 => ge~13.OUTPUTSELECT
set0 => ge~14.OUTPUTSELECT
set0 => ge~15.OUTPUTSELECT
set1 => shi~20.OUTPUTSELECT
set1 => shi~21.OUTPUTSELECT
set1 => shi~22.OUTPUTSELECT
set1 => shi~23.OUTPUTSELECT
set1 => ge[0]~reg0.ENA
set1 => ge[1]~reg0.ENA
set1 => ge[2]~reg0.ENA
set1 => ge[3]~reg0.ENA
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[0] <= ge[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[1] <= ge[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[2] <= ge[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[3] <= ge[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[0] <= shi[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[1] <= shi[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[2] <= shi[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[3] <= shi[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|timer|sec:24
clk => co~reg0.CLK
clk => shi[0]~reg0.CLK
clk => shi[1]~reg0.CLK
clk => shi[2]~reg0.CLK
clk => shi[3]~reg0.CLK
clk => ge[0]~reg0.CLK
clk => ge[1]~reg0.CLK
clk => ge[2]~reg0.CLK
clk => ge[3]~reg0.CLK
clr => shi[0]~reg0.ACLR
clr => shi[1]~reg0.ACLR
clr => shi[2]~reg0.ACLR
clr => shi[3]~reg0.ACLR
clr => ge[0]~reg0.ACLR
clr => ge[1]~reg0.ACLR
clr => ge[2]~reg0.ACLR
clr => ge[3]~reg0.ACLR
set0 => shi~16.OUTPUTSELECT
set0 => shi~17.OUTPUTSELECT
set0 => shi~18.OUTPUTSELECT
set0 => shi~19.OUTPUTSELECT
set0 => ge~12.OUTPUTSELECT
set0 => ge~13.OUTPUTSELECT
set0 => ge~14.OUTPUTSELECT
set0 => ge~15.OUTPUTSELECT
set1 => shi~20.OUTPUTSELECT
set1 => shi~21.OUTPUTSELECT
set1 => shi~22.OUTPUTSELECT
set1 => shi~23.OUTPUTSELECT
set1 => ge[0]~reg0.ENA
set1 => ge[1]~reg0.ENA
set1 => ge[2]~reg0.ENA
set1 => ge[3]~reg0.ENA
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[0] <= ge[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[1] <= ge[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[2] <= ge[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ge[3] <= ge[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[0] <= shi[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[1] <= shi[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[2] <= shi[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
shi[3] <= shi[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE