decoder.rpt
来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· RPT 代码 · 共 598 行 · 第 1/2 页
RPT
598 行
Device-Specific Information: e:\kai\timer\decoder.rpt
decoder
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', location is LC020, type is output.
q0 = LCELL( _EQ001 $ GND);
_EQ001 = _LC008 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is 'q1'
-- Equation name is 'q1', location is LC024, type is output.
q1 = LCELL( _EQ002 $ _EQ003);
_EQ002 = _LC006 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_EQ003 = !d0 & !d1 & !d2 & !d3;
-- Node name is 'q2'
-- Equation name is 'q2', location is LC026, type is output.
q2 = LCELL( _EQ004 $ _EQ005);
_EQ004 = _LC005 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_EQ005 = !d0 & !d1 & !d2 & !d3;
-- Node name is 'q3'
-- Equation name is 'q3', location is LC027, type is output.
q3 = LCELL( _EQ006 $ _EQ007);
_EQ006 = _LC004 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_EQ007 = !d0 & !d1 & !d2 & !d3;
-- Node name is 'q4'
-- Equation name is 'q4', location is LC028, type is output.
q4 = LCELL( _EQ008 $ _EQ009);
_EQ008 = _LC002 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_EQ009 = !d0 & !d1 & !d2 & !d3;
-- Node name is 'q5'
-- Equation name is 'q5', location is LC031, type is output.
q5 = LCELL( _EQ010 $ _EQ011);
_EQ010 = _LC001 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_EQ011 = !d0 & !d1 & !d2 & !d3;
-- Node name is 'q6'
-- Equation name is 'q6', location is LC032, type is output.
q6 = LCELL( _EQ012 $ GND);
_EQ012 = !d0 & !d1 & !d2 & !d3
# _LC029 & _X001 & _X002;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~326~1'
-- Equation name is '~326~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ013 $ VCC);
_EQ013 = !d0 & !d1 & d2 & !d3
# !d1 & !d2 & !d3 & !_LC018
# d2 & d3 & !_LC018
# d1 & d3 & !_LC018;
-- Node name is '~350~1~2'
-- Equation name is '~350~1~2', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ014 $ GND);
_EQ014 = !d0 & !d1 & !d3 & !_LC018 & _X001
# !d0 & !d1 & d2 & !_LC018 & _X001
# d1 & d3 & !_LC018 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~350~1'
-- Equation name is '~350~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ015 $ VCC);
_EQ015 = d0 & !d1 & !d2 & !d3 & _X001
# !d0 & !d1 & d2 & !d3 & _X001
# !d1 & !d2 & !d3 & !_LC018 & _X001
# d2 & d3 & !_LC018 & _X001
# _LC017;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~380~1'
-- Equation name is '~380~1', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ016 $ VCC);
_EQ016 = d0 & !d1 & d2 & !d3 & _X002
# !d0 & d1 & d2 & !d3 & _X002
# !d1 & !d2 & !d3 & !_LC019 & _X002
# d2 & d3 & !_LC019 & _X002
# d1 & d3 & !_LC019 & _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~383~1'
-- Equation name is '~383~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ017 $ VCC);
_EQ017 = !_LC001 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~413~1'
-- Equation name is '~413~1', location is LC002, type is buried.
-- synthesized logic cell
_LC002 = LCELL( _EQ018 $ VCC);
_EQ018 = !d0 & d1 & !d2 & !d3 & _X002
# !d1 & !d2 & !d3 & !_LC021 & _X002
# d2 & d3 & !_LC021 & _X002
# d1 & d3 & !_LC021 & _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~416~1'
-- Equation name is '~416~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ019 $ VCC);
_EQ019 = !_LC002 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~446~1'
-- Equation name is '~446~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ020 $ _EQ021);
_EQ020 = d0 & d1 & d2 & !d3 & _X002
# !d0 & !d1 & d2 & !d3 & _X002
# !d1 & !d2 & !d3 & !_LC022 & _X002
# d3 & !_LC022 & _X002 & _X003;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
_X003 = EXP(!d1 & !d2);
_EQ021 = _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~449~1'
-- Equation name is '~449~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ022 $ VCC);
_EQ022 = !_LC004 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~479~1'
-- Equation name is '~479~1', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ023 $ GND);
_EQ023 = !d0 & !d1 & !d2 & d3 & _X002
# !d1 & !d2 & !d3 & _LC023 & _X002
# d2 & d3 & _LC023 & _X002
# d1 & d3 & _LC023 & _X002
# !d0 & d1 & !d3 & _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~482~1'
-- Equation name is '~482~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ024 $ VCC);
_EQ024 = !_LC005 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~512~1'
-- Equation name is '~512~1', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ025 $ GND);
_EQ025 = !d0 & d2 & !d3 & _X002
# !d1 & !d2 & d3 & _X002
# !d1 & d2 & !d3 & _X002
# d3 & _LC025 & _X002
# !d1 & _LC025 & _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~515~1'
-- Equation name is '~515~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ026 $ VCC);
_EQ026 = !_LC006 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Node name is '~545~1'
-- Equation name is '~545~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ027 $ _EQ028);
_EQ027 = d0 & d1 & d2 & !d3 & _X002
# !d1 & !d2 & !d3 & !_LC030 & _X002
# d2 & d3 & !_LC030 & _X002
# d1 & d3 & !_LC030 & _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
_EQ028 = _X002;
_X002 = EXP( d0 & !d1 & !d2 & !d3);
-- Node name is '~548~1'
-- Equation name is '~548~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ029 $ GND);
_EQ029 = _LC008 & _X001;
_X001 = EXP(!d0 & !d1 & !d2 & !d3);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs A, B
Project Information e:\kai\timer\decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,002K
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