sec.rpt

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                                       Logic cells placed in LAB 'B'
        +----------------------------- LC26 co
        | +--------------------------- LC22 ge0
        | | +------------------------- LC20 ge1
        | | | +----------------------- LC18 ge2
        | | | | +--------------------- LC17 ge3
        | | | | | +------------------- LC32 |LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node1
        | | | | | | +----------------- LC31 |LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node3
        | | | | | | | +--------------- LC30 |LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node1
        | | | | | | | | +------------- LC29 |LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | | +----------- LC27 |LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node1
        | | | | | | | | | | +--------- LC25 |LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | | | | +------- LC19 shi0
        | | | | | | | | | | | | +----- LC21 shi1
        | | | | | | | | | | | | | +--- LC23 shi2
        | | | | | | | | | | | | | | +- LC24 shi3
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * * * * * - - - - - - * * * * | - * | <-- ge0
LC20 -> * - * * * - - - - - - * * * * | - * | <-- ge1
LC18 -> * - * * * - - - - - - * * * * | - * | <-- ge2
LC17 -> * - * - * - - - - - - * * * * | - * | <-- ge3
LC32 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node1
LC31 -> - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node3
LC30 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node1
LC29 -> - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node3
LC27 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node1
LC25 -> - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node3
LC19 -> * - - - - * * * * * * * * * * | - * | <-- shi0
LC21 -> * - - - - * * * * * * - * * * | - * | <-- shi1
LC23 -> * - - - - - * - * - * - * * * | - * | <-- shi2
LC24 -> * - - - - - * - * - * - * * * | - * | <-- shi3

Pin
4    -> * * * * * - - - - - - * * * * | - * | <-- clk
1    -> * - - - - - - - - - - - - - - | - * | <-- clr
5    -> * - - - - - - - - - - * * * * | - * | <-- set0
6    -> * * * * * - - - - - - * * * * | - * | <-- set1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              e:\kai\timer\sec.rpt
sec

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
set0     : INPUT;
set1     : INPUT;

-- Node name is 'co' = ':5' 
-- Equation name is 'co', type is output 
 co      = TFFE( _EQ001, !clk,  VCC,  VCC,  VCC);
  _EQ001 =  clr &  ge0 & !ge1 & !ge2 &  ge3 &  set0 &  set1 &  shi0 & !shi1 & 
              shi2 & !shi3
         #  clr &  ge0 & !ge1 & !ge2 &  ge3 &  set0 &  set1 & !shi0 &  shi1 & 
             !shi2 & !shi3;

-- Node name is 'ge0' = ':13' 
-- Equation name is 'ge0', type is output 
 ge0     = TFFE( set1, !clk, GLOBAL( clr),  VCC,  VCC);

-- Node name is 'ge1' = ':11' 
-- Equation name is 'ge1', type is output 
 ge1     = TFFE( _EQ002, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ002 =  ge0 & !ge1 &  ge2 &  set1
         #  ge0 & !ge1 & !ge3 &  set1
         #  ge0 &  ge1 &  set1;

-- Node name is 'ge2' = ':9' 
-- Equation name is 'ge2', type is output 
 ge2     = TFFE( _EQ003, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ003 =  ge0 &  ge1 &  set1;

-- Node name is 'ge3' = ':7' 
-- Equation name is 'ge3', type is output 
 ge3     = TFFE( _EQ004, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ004 =  ge0 & !ge1 & !ge2 &  ge3 &  set1
         #  ge0 &  ge1 &  ge2 &  set1;

-- Node name is 'shi0' = ':21' 
-- Equation name is 'shi0', type is output 
 shi0    = TFFE( _EQ005, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ005 =  ge0 & !ge1 & !ge2 &  ge3 &  set0
         # !set1;

-- Node name is 'shi1' = ':19' 
-- Equation name is 'shi1', type is output 
 shi1    = DFFE( _EQ006 $  _EQ007, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ006 =  ge0 & !ge1 & !ge2 &  ge3 & !_LC027 &  set0 &  set1 &  _X001
         #  set1 &  shi0 & !shi1 &  shi2 & !shi3
         #  set1 & !shi1 &  _X002;
  _X001  = EXP(!shi0 & !shi2 & !shi3);
  _X002  = EXP( ge0 & !ge1 & !ge2 &  ge3 &  _LC027 &  set0);
  _EQ007 =  _X003 &  _X004 &  _X005;
  _X003  = EXP( ge0 & !ge1 & !ge2 &  ge3 & !_LC030 &  set0 &  set1 & !shi0 & 
              shi1 & !shi2 & !shi3);
  _X004  = EXP(!set1 &  shi0 & !shi1 & !shi2 &  shi3);
  _X005  = EXP(!_LC032 & !set1);

-- Node name is 'shi2' = ':17' 
-- Equation name is 'shi2', type is output 
 shi2    = TFFE( _EQ008, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ008 =  ge0 & !ge1 & !ge2 &  ge3 &  set0 &  set1 &  shi0 & !shi1 &  shi2 & 
             !shi3
         #  ge0 & !ge1 & !ge2 &  ge3 &  set0 &  shi0 &  shi1
         # !set1 &  shi0 &  shi1;

-- Node name is 'shi3' = ':15' 
-- Equation name is 'shi3', type is output 
 shi3    = DFFE( _EQ009 $  _EQ010, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ009 =  ge0 & !ge1 & !ge2 &  ge3 & !_LC025 &  set0 &  set1 &  shi0 & 
              _X004 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013 &  _X014
         #  ge0 & !ge1 & !ge2 &  ge3 & !_LC025 &  set0 &  set1 &  shi2 & 
              _X004 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013 &  _X014
         #  ge0 & !ge1 & !ge2 &  ge3 & !_LC025 &  set0 &  set1 &  shi3 & 
              _X004 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013 &  _X014;
  _X004  = EXP(!set1 &  shi0 & !shi1 & !shi2 &  shi3);
  _X006  = EXP( ge0 & !ge1 & !ge2 &  ge3 & !_LC025 &  set0 &  set1 & !shi1);
  _X007  = EXP(!set0 &  set1 & !shi3);
  _X008  = EXP(!_LC029 &  set1 & !shi0 &  shi1 & !shi2 & !shi3);
  _X009  = EXP( set1 &  shi0 & !shi1 &  shi2 & !shi3);
  _X010  = EXP( ge1 &  set1 & !shi3);
  _X011  = EXP( ge2 &  set1 & !shi3);
  _X012  = EXP(!ge0 &  set1 & !shi3);
  _X013  = EXP(!ge3 &  set1 & !shi3);
  _X014  = EXP(!_LC031 & !set1);
  _EQ010 =  _X004 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013 &  _X014;
  _X004  = EXP(!set1 &  shi0 & !shi1 & !shi2 &  shi3);
  _X006  = EXP( ge0 & !ge1 & !ge2 &  ge3 & !_LC025 &  set0 &  set1 & !shi1);
  _X007  = EXP(!set0 &  set1 & !shi3);
  _X008  = EXP(!_LC029 &  set1 & !shi0 &  shi1 & !shi2 & !shi3);
  _X009  = EXP( set1 &  shi0 & !shi1 &  shi2 & !shi3);
  _X010  = EXP( ge1 &  set1 & !shi3);
  _X011  = EXP( ge2 &  set1 & !shi3);
  _X012  = EXP(!ge0 &  set1 & !shi3);
  _X013  = EXP(!ge3 &  set1 & !shi3);
  _X014  = EXP(!_LC031 & !set1);

-- Node name is '|LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried 
_LC032   = LCELL( shi1 $  shi0);

-- Node name is '|LPM_ADD_SUB:189|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried 
_LC031   = LCELL( shi3 $  _EQ011);
  _EQ011 =  shi0 &  shi1 &  shi2;

-- Node name is '|LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( shi1 $  shi0);

-- Node name is '|LPM_ADD_SUB:352|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( shi3 $  _EQ012);
  _EQ012 =  shi0 &  shi1 &  shi2;

-- Node name is '|LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( shi1 $  shi0);

-- Node name is '|LPM_ADD_SUB:378|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( shi3 $  _EQ013);
  _EQ013 =  shi0 &  shi1 &  shi2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       e:\kai\timer\sec.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,704K