maxplusii_to_quartus_name_mapping.txt

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"
 -- DATE "06/14/2005 22:14:16"

Conversion results for timer
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |q0                   | q[0]                 |
| |q1                   | q[1]                 |
| |q2                   | q[2]                 |
| |q3                   | q[3]                 |
| |q4                   | q[4]                 |
| |q5                   | q[5]                 |
| |q6                   | q[6]                 |
| |sel0                 | sel[0]               |
| |sel1                 | sel[1]               |
| |sel2                 | sel[2]               |
| |sel3                 | sel[3]               |
| |sel4                 | sel[4]               |
| |sel5                 | sel[5]               |
| |sel6                 | sel[6]               |
| |sel7                 | sel[7]               |
+-----------------------+----------------------+