fre_100.rpt

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t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          e:\kai\timer\fre_100.rpt
fre_100

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC27 |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node1
        | +------------------- LC26 |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node2
        | | +----------------- LC25 |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node3
        | | | +--------------- LC24 |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node5
        | | | | +------------- LC23 q
        | | | | | +----------- LC21 a5
        | | | | | | +--------- LC20 a4
        | | | | | | | +------- LC19 a3
        | | | | | | | | +----- LC18 a2
        | | | | | | | | | +--- LC17 a1
        | | | | | | | | | | +- LC22 a0
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node1
LC26 -> - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node3
LC24 -> - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node5
LC21 -> - - - * * * * * * * * | - * | <-- a5
LC20 -> - - - * * * * * * * * | - * | <-- a4
LC19 -> - - * * * * * * * * * | - * | <-- a3
LC18 -> - * * * * * * * * * * | - * | <-- a2
LC17 -> * * * * * * * * * * * | - * | <-- a1
LC22 -> * * * * - - * - - - * | - * | <-- a0

Pin
43   -> - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          e:\kai\timer\fre_100.rpt
fre_100

** EQUATIONS **

clk      : INPUT;

-- Node name is ':9' = 'a0' 
-- Equation name is 'a0', location is LC022, type is buried.
a0       = DFFE( _EQ001 $ !a5, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !a0 & !a1 & !a2 & !a3 &  a5
         # !a0 & !a4 &  a5
         #  a0 & !a5;

-- Node name is ':8' = 'a1' 
-- Equation name is 'a1', location is LC017, type is buried.
a1       = DFFE( _EQ002 $  _LC027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  a3 &  a4 &  a5 &  _LC027
         #  a2 &  a4 &  a5 &  _LC027
         #  a1 &  a4 &  a5 &  _LC027;

-- Node name is ':7' = 'a2' 
-- Equation name is 'a2', location is LC018, type is buried.
a2       = DFFE( _EQ003 $  _LC026, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  a3 &  a4 &  a5 &  _LC026
         #  a2 &  a4 &  a5 &  _LC026
         #  a1 &  a4 &  a5 &  _LC026;

-- Node name is ':6' = 'a3' 
-- Equation name is 'a3', location is LC019, type is buried.
a3       = DFFE( _EQ004 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  a3 &  a4 &  a5 &  _LC025
         #  a2 &  a4 &  a5 &  _LC025
         #  a1 &  a4 &  a5 &  _LC025;

-- Node name is ':5' = 'a4' 
-- Equation name is 'a4', location is LC020, type is buried.
a4       = TFFE(!_EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !a1 & !a2 & !a3 &  a4 &  _X001
         #  a4 & !a5 &  _X001
         # !a4 &  _X001;
  _X001  = EXP( a0 &  a1 &  a2 &  a3);

-- Node name is ':4' = 'a5' 
-- Equation name is 'a5', location is LC021, type is buried.
a5       = TFFE(!_EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !a1 & !a2 & !a3 &  a5 &  _LC024
         # !a4 &  a5 &  _LC024
         # !a5 & !_LC024;

-- Node name is 'q' = ':2' 
-- Equation name is 'q', type is output 
 q       = TFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  a3 &  a4 &  a5
         #  a2 &  a4 &  a5
         #  a1 &  a4 &  a5;

-- Node name is '|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( a1 $  a0);

-- Node name is '|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( a2 $  _EQ008);
  _EQ008 =  a0 &  a1;

-- Node name is '|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( a3 $  _EQ009);
  _EQ009 =  a0 &  a1 &  a2;

-- Node name is '|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( a5 $  _EQ010);
  _EQ010 =  a0 &  a1 &  a2 &  a3 &  a4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   e:\kai\timer\fre_100.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,133K