contr.rpt
来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· RPT 代码 · 共 641 行 · 第 1/2 页
RPT
641 行
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * - - - - - - - - - - - * - - - | - * | <-- clkh
LC23 -> - * - - - - - - - - - - - * - - | - * | <-- clkm
LC18 -> - - * - - - - - - - - - - - - * | - * | <-- clkmm
LC17 -> - - - * - - - - - - - - - - * - | - * | <-- clks
LC19 -> - - - - - * - - - - - - - - - - | - * | <-- s0
LC21 -> - - - - - - * - - - - - - - - - | - * | <-- s1
LC24 -> - - - - - - - * - - - - - - - - | - * | <-- s2
LC27 -> - - - - - - - - * - - - - - - - | - * | <-- s3
LC31 -> - - - - - - - - - * - - - - - - | - * | <-- s4
LC29 -> - - - - - - - - - - * - - - - - | - * | <-- s5
LC25 -> * * * * * * * * * * * * * * * * | * * | <-- tem0
LC28 -> * - - - - - - - - - - - - - - - | - * | <-- ~730~1~2
LC26 -> - * - - - - - - - - - - - - - - | - * | <-- ~736~1~2
LC32 -> - - - * - - - - - - - - - - - - | - * | <-- ~742~1~2
LC30 -> - - * - - - - - - - - - - - - - | - * | <-- ~748~1~2
Pin
11 -> - - * - - - - - - - - - - - - * | - * | <-- clk
8 -> - - - * - - - - - - - - - - * - | - * | <-- clk1
6 -> - * - - - - - - - - - - - * - - | - * | <-- clk2
5 -> * - - - - - - - - - - - * - - - | - * | <-- clk3
4 -> * * * * - * * * * * * - * * * * | - * | <-- pause
43 -> - - - - - - - - - - - - - - - - | - - | <-- sel
9 -> * * - * - - - - - - - - * * * - | - * | <-- set
LC2 -> * * * * * * * * * * * * * * * * | * * | <-- tem2
LC1 -> * * * * * * * * * * * * * * * * | * * | <-- tem1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\eda\timer\contr.rpt
contr
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
clk2 : INPUT;
clk3 : INPUT;
pause : INPUT;
sel : INPUT;
set : INPUT;
-- Node name is 'clkh' = '~730~1'
-- Equation name is 'clkh', location is LC022, type is output.
clkh = LCELL( _EQ001 $ _EQ002);
_EQ001 = pause & !set & !tem0 & tem1 & tem2 & _X001 & _X002 & _X003 &
_X004 & _X005
# pause & !set & tem0 & !tem1 & tem2 & _X001 & _X002 & _X003 &
_X004 & _X005
# !clk3 & pause & !tem0 & !tem1 & !tem2 & _X001 & _X002 & _X003 &
_X004 & _X005
# _LC028;
_X001 = EXP(!clkh & !set & tem2);
_X002 = EXP(!clkh & tem0 & tem1);
_X003 = EXP(!clkh & tem1 & !tem2);
_X004 = EXP(!clkh & tem0 & !tem2);
_X005 = EXP(!clkh & !pause);
_EQ002 = _X001 & _X002 & _X003 & _X004 & _X005;
_X001 = EXP(!clkh & !set & tem2);
_X002 = EXP(!clkh & tem0 & tem1);
_X003 = EXP(!clkh & tem1 & !tem2);
_X004 = EXP(!clkh & tem0 & !tem2);
_X005 = EXP(!clkh & !pause);
-- Node name is 'clkm' = '~736~1'
-- Equation name is 'clkm', location is LC023, type is output.
clkm = LCELL( _EQ003 $ _EQ004);
_EQ003 = pause & !set & tem0 & tem1 & !tem2 & _X006 & _X007 & _X008
# pause & !set & !tem0 & !tem1 & tem2 & _X006 & _X007 & _X008
# !clk2 & pause & !tem0 & !tem1 & !tem2 & _X006 & _X007 & _X008
# _LC026;
_X006 = EXP(!clkm & !tem0 & tem1);
_X007 = EXP(!clkm & tem0 & !tem1);
_X008 = EXP(!clkm & !pause);
_EQ004 = _X006 & _X007 & _X008;
_X006 = EXP(!clkm & !tem0 & tem1);
_X007 = EXP(!clkm & tem0 & !tem1);
_X008 = EXP(!clkm & !pause);
-- Node name is 'clkmm' = '~748~1'
-- Equation name is 'clkmm', location is LC018, type is output.
clkmm = LCELL( _EQ005 $ GND);
_EQ005 = clk & pause & !tem0 & !tem1 & !tem2
# clkmm & tem2
# clkmm & tem1
# clkmm & tem0
# _LC030;
-- Node name is 'clks' = '~742~1'
-- Equation name is 'clks', location is LC017, type is output.
clks = LCELL( _EQ006 $ VCC);
_EQ006 = pause & !set & !tem0 & tem1 & !tem2
# pause & !set & tem0 & !tem1 & !tem2
# !clk1 & pause & !tem0 & !tem1 & !tem2
# !clks & tem0 & tem1
# _LC032;
-- Node name is 's0' = '~694~1'
-- Equation name is 's0', location is LC019, type is output.
s0 = LCELL( _EQ007 $ VCC);
_EQ007 = pause & !tem0 & tem1 & tem2
# !s0 & tem1 & tem2
# !pause & !s0;
-- Node name is 's1' = '~700~1'
-- Equation name is 's1', location is LC021, type is output.
s1 = LCELL( _EQ008 $ VCC);
_EQ008 = pause & tem0 & !tem1 & tem2
# !s1 & tem0 & tem2
# !pause & !s1;
-- Node name is 's2' = '~706~1'
-- Equation name is 's2', location is LC024, type is output.
s2 = LCELL( _EQ009 $ VCC);
_EQ009 = !s2 & tem0 & tem1 & tem2
# pause & !tem0 & !tem1 & tem2
# !pause & !s2
# !s2 & !tem0 & !tem1 & tem2;
-- Node name is 's3' = '~712~1'
-- Equation name is 's3', location is LC027, type is output.
s3 = LCELL( _EQ010 $ VCC);
_EQ010 = pause & tem0 & tem1 & !tem2
# !s3 & tem0 & tem1
# !pause & !s3;
-- Node name is 's4' = '~718~1'
-- Equation name is 's4', location is LC031, type is output.
s4 = LCELL( _EQ011 $ VCC);
_EQ011 = !s4 & tem0 & tem1 & tem2
# pause & !tem0 & tem1 & !tem2
# !pause & !s4
# !s4 & !tem0 & tem1 & !tem2;
-- Node name is 's5' = '~724~1'
-- Equation name is 's5', location is LC029, type is output.
s5 = LCELL( _EQ012 $ VCC);
_EQ012 = !s5 & tem0 & tem1 & tem2
# pause & tem0 & !tem1 & !tem2
# !pause & !s5
# !s5 & tem0 & !tem1 & !tem2;
-- Node name is ':20' = 'tem0'
-- Equation name is 'tem0', location is LC025, type is buried.
tem0 = TFFE(!_EQ013, GLOBAL(!sel), VCC, VCC, VCC);
_EQ013 = !tem0 & tem1 & tem2;
-- Node name is ':19' = 'tem1'
-- Equation name is 'tem1', location is LC001, type is buried.
tem1 = DFFE( _EQ014 $ _LC004, GLOBAL(!sel), VCC, VCC, VCC);
_EQ014 = _LC004 & !tem0 & tem1 & tem2;
-- Node name is ':18' = 'tem2'
-- Equation name is 'tem2', location is LC002, type is buried.
tem2 = DFFE( _EQ015 $ _LC020, GLOBAL(!sel), VCC, VCC, VCC);
_EQ015 = _LC020 & !tem0 & tem1 & tem2;
-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( tem1 $ tem0);
-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( tem2 $ _EQ016);
_EQ016 = tem0 & tem1;
-- Node name is '~730~1~2'
-- Equation name is '~730~1~2', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ017 $ GND);
_EQ017 = !clkh & pause & !set & !tem0 & tem2 & _X001 & _X002 & _X003 &
_X004 & _X005
# !clkh & pause & !set & !tem1 & tem2 & _X001 & _X002 & _X003 &
_X004 & _X005
# !clkh & !clk3 & pause & !tem0 & !tem1 & _X001 & _X002 & _X003 &
_X004 & _X005
# !clkh & !tem0 & !tem1 & tem2 & _X001 & _X002 & _X003 & _X004 &
_X005;
_X001 = EXP(!clkh & !set & tem2);
_X002 = EXP(!clkh & tem0 & tem1);
_X003 = EXP(!clkh & tem1 & !tem2);
_X004 = EXP(!clkh & tem0 & !tem2);
_X005 = EXP(!clkh & !pause);
-- Node name is '~736~1~2'
-- Equation name is '~736~1~2', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ018 $ GND);
_EQ018 = !clkm & pause & !set & tem0 & tem1 & _X006 & _X007 & _X008
# !clk2 & pause & !set & !tem0 & !tem1 & _X006 & _X007 & _X008
# !clkm & pause & !set & !tem0 & tem2 & _X006 & _X007 & _X008
# !clkm & tem1 & tem2 & _X006 & _X007 & _X008;
_X006 = EXP(!clkm & !tem0 & tem1);
_X007 = EXP(!clkm & tem0 & !tem1);
_X008 = EXP(!clkm & !pause);
-- Node name is '~742~1~2'
-- Equation name is '~742~1~2', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ019 $ GND);
_EQ019 = !clk1 & pause & !set & !tem0 & !tem2
# !clks & pause & !set & tem1 & !tem2
# !clk1 & pause & !set & !tem1 & !tem2
# !clks & pause & !set & tem0 & !tem2
# !clks & _X009;
_X009 = EXP( pause & !tem2);
-- Node name is '~748~1~2'
-- Equation name is '~748~1~2', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ020 $ GND);
_EQ020 = clk & clkmm & pause & !tem0 & !tem1
# clk & clkmm & pause & !tem0 & !tem2
# clk & clkmm & pause & !tem1 & !tem2
# clk & clkmm & !tem0 & !tem1 & !tem2
# clkmm & !pause;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\eda\timer\contr.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,519K
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?