timer.tan.rpt

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

Timing Analyzer report for timer
Tue Jun 14 23:19:41 2005
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Hold: 'clk'
  7. tsu
  8. tco
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                         ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------+----------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                       ; To             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------+----------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; -4.651 ns                        ; set                        ; d_ff:18|q3     ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 35.230 ns                        ; decoder:2|q[4]             ; q[4]           ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 5.991 ns                         ; pause                      ; d_ff:18|q1     ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 61.87 MHz ( period = 16.163 ns ) ; hour:17|shi[1]             ; decoder:2|q[6] ; clk        ; clk      ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; decoder_dynamic:13|temp[0] ; decoder:2|q[4] ; clk        ; clk      ; 321          ;
; Total number of failed paths ;                                          ;               ;                                  ;                            ;                ;            ;          ; 321          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------+----------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;