decoder_dynamic.vhd

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder_dynamic is
port(clk:in std_logic;
     h1,h0,m1,m0,s0,s1,x0,x1:in std_logic_vector(3 downto 0);
     q:out std_logic_vector(3 downto 0);
     sel:out std_logic_vector(7 downto 0));
end;
architecture  dec of decoder_dynamic is
signal temp:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
  if temp="111" then
   temp<="000";
   else temp<=temp+'1';
   end if;
end if;
end process;
process(temp)
begin 
case temp is
when"000"=>q<=h1;sel<="10000000";
when"001"=>q<=h0;sel<="01000000";
when"010"=>q<=m1;sel<="00100000";
when"011"=>q<=m0;sel<="00010000";
when"100"=>q<=s1;sel<="00001000";
when"101"=>q<=s0;sel<="00000100";
when"110"=>q<=x1;sel<="00000010";
when"111"=>q<=x0;sel<="00000001";
when others=>null;
end case;
end process;
end;