freq_divider.vhd

来自「一个简单的分频器代码,可以套用来作其他频率的分频」· VHDL 代码 · 共 60 行

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-- Company: 
-- Engineer:
--
-- Create Date:    14:25:12 11/23/07
-- Design Name:    
-- Module Name:    freq-divider - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freq_divider is
    Port ( clk : in std_logic;
           out1 : out std_logic;
           out2 : out std_logic);
end freq_divider;

architecture Behavioral of freq_divider is
	signal out01:std_logic:='0';
	signal out02:std_logic:='0';
	signal count1: integer range 0 to 7;
begin
	process(clk)
		variable count2: integer range 0 to 7;
	begin
		if(clk'event and clk='1') then
			count1<=count1+1;
			count2:=count2+1;
			if(count1=3) then
				out01<= not out01;
				count1<=0;
			end if;
			if(count2=4) then
				out02<= not out02;
				count2:=0;
			end if;
		end if;
	end process;
	out1 <= out01;	
	out2 <= out02;	
end Behavioral;