📄 xianshi.rpt
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_EQ011 = _LC1_B13 & _LC1_B23 & _LC2_B13 & _LC2_B16
# _LC1_B13 & !_LC2_B13 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|E~3' from file "bcd7.tdf" line 25, column 17
-- Equation name is '_LC7_B17', type is buried
-- synthesized logic cell
_LC7_B17 = LCELL( _EQ012);
_EQ012 = !_LC1_B13 & !_LC2_B13 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|F' from file "bcd7.tdf" line 25, column 19
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ013);
_EQ013 = !_LC1_B23 & !_LC2_B16
# !_LC1_B13 & !_LC1_B23 & _LC2_B13
# _LC2_B13 & !_LC2_B16
# _LC1_B13 & !_LC2_B13
# _LC1_B13 & _LC1_B23
# _LC1_B13 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|F~1' from file "bcd7.tdf" line 25, column 19
-- Equation name is '_LC5_B17', type is buried
-- synthesized logic cell
_LC5_B17 = LCELL( _EQ014);
_EQ014 = _LC1_B13 & !_LC2_B13 & !_LC2_B16
# _LC1_B13 & !_LC1_B23 & !_LC2_B13
# !_LC1_B13 & !_LC1_B23 & _LC2_B13 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|G' from file "bcd7.tdf" line 25, column 21
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ015);
_EQ015 = !_LC1_B13 & !_LC1_B23 & _LC2_B13
# !_LC1_B13 & _LC2_B13 & !_LC2_B16
# _LC1_B13 & !_LC2_B13
# _LC1_B13 & _LC1_B23
# _LC1_B23 & !_LC2_B13
# _LC1_B13 & _LC2_B16;
-- Node name is '|mulx:41|bcd7:1|~57~1' from file "bcd7.tdf" line 11, column 5
-- Equation name is '_LC3_B17', type is buried
-- synthesized logic cell
_LC3_B17 = LCELL( _EQ016);
_EQ016 = !_LC1_B13 & !_LC2_B13;
-- Node name is '|mulx:41|bcd7:1|:203' from file "bcd7.tdf" line 21, column 5
-- Equation name is '_LC2_B21', type is buried
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ017);
_EQ017 = _LC1_B13 & _LC1_B23 & !_LC2_B13 & _LC2_B16;
-- Node name is '|mulx:41|bcd7:1|:232' from file "bcd7.tdf" line 23, column 5
-- Equation name is '_LC6_B21', type is buried
!_LC6_B21 = _LC6_B21~NOT;
_LC6_B21~NOT = LCELL( _EQ018);
_EQ018 = _LC1_B13 & !_LC1_B23 & _LC2_B13 & _LC2_B16;
-- Node name is '|mulx:41|mulx6:2|SS~1' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE( _LC1_B16, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|SS~2' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = DFFE( _LC7_B23, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|SS~3' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = DFFE( _LC4_B23, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|SS~4' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = DFFE( _LC8_B23, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|SS~5' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = DFFE(!_LC3_B13, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|SS~6' from file "mulx6.tdf" line 5, column 10
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = DFFE(!_LC8_B16, GLOBAL( STRUCK), VCC, VCC, VCC);
-- Node name is '|mulx:41|mulx6:2|~122~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC3_B23', type is buried
-- synthesized logic cell
_LC3_B23 = LCELL( _EQ019);
_EQ019 = B1 & _LC4_B23
# A5 & _LC8_B23;
-- Node name is '|mulx:41|mulx6:2|~122~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC4_B16', type is buried
-- synthesized logic cell
_LC4_B16 = LCELL( _EQ020);
_EQ020 = C1 & _LC1_B16
# B5 & _LC7_B23;
-- Node name is '|mulx:41|mulx6:2|~122~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC5_B16', type is buried
-- synthesized logic cell
_LC5_B16 = LCELL( _EQ021);
_EQ021 = A1 & !_LC3_B13
# C5 & _LC8_B16;
-- Node name is '|mulx:41|mulx6:2|:122' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ022);
_EQ022 = _LC3_B23
# _LC4_B16
# _LC5_B16;
-- Node name is '|mulx:41|mulx6:2|~124~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC5_B23', type is buried
-- synthesized logic cell
!_LC5_B23 = _LC5_B23~NOT;
_LC5_B23~NOT = LCELL( _EQ023);
_EQ023 = !A2 & !C6
# !C6 & _LC3_B13
# !A2 & !_LC8_B16
# _LC3_B13 & !_LC8_B16;
-- Node name is '|mulx:41|mulx6:2|~124~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC3_B16', type is buried
-- synthesized logic cell
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ024);
_EQ024 = !B6 & !C2
# !B6 & !_LC1_B16
# !C2 & !_LC7_B23
# !_LC1_B16 & !_LC7_B23;
-- Node name is '|mulx:41|mulx6:2|~124~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC6_B23', type is buried
-- synthesized logic cell
!_LC6_B23 = _LC6_B23~NOT;
_LC6_B23~NOT = LCELL( _EQ025);
_EQ025 = !A6 & !B2
# !A6 & !_LC4_B23
# !B2 & !_LC8_B23
# !_LC4_B23 & !_LC8_B23;
-- Node name is '|mulx:41|mulx6:2|:124' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC1_B23', type is buried
!_LC1_B23 = _LC1_B23~NOT;
_LC1_B23~NOT = LCELL( _EQ026);
_EQ026 = !_LC3_B16 & !_LC5_B23 & !_LC6_B23;
-- Node name is '|mulx:41|mulx6:2|~126~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC4_B13', type is buried
-- synthesized logic cell
_LC4_B13 = LCELL( _EQ027);
_EQ027 = B3 & _LC4_B23
# A7 & _LC8_B23;
-- Node name is '|mulx:41|mulx6:2|~126~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC5_B13', type is buried
-- synthesized logic cell
_LC5_B13 = LCELL( _EQ028);
_EQ028 = C3 & _LC1_B16
# B7 & _LC7_B23;
-- Node name is '|mulx:41|mulx6:2|~126~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC6_B13', type is buried
-- synthesized logic cell
_LC6_B13 = LCELL( _EQ029);
_EQ029 = A3 & !_LC3_B13
# C7 & _LC8_B16;
-- Node name is '|mulx:41|mulx6:2|:126' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ030);
_EQ030 = _LC4_B13
# _LC5_B13
# _LC6_B13;
-- Node name is '|mulx:41|mulx6:2|~128~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC2_B23', type is buried
-- synthesized logic cell
!_LC2_B23 = _LC2_B23~NOT;
_LC2_B23~NOT = LCELL( _EQ031);
_EQ031 = B4 & _LC4_B23
# A8 & _LC8_B23;
-- Node name is '|mulx:41|mulx6:2|~128~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC7_B13', type is buried
-- synthesized logic cell
!_LC7_B13 = _LC7_B13~NOT;
_LC7_B13~NOT = LCELL( _EQ032);
_EQ032 = C4 & _LC1_B16
# B8 & _LC7_B23;
-- Node name is '|mulx:41|mulx6:2|~128~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC8_B13', type is buried
-- synthesized logic cell
!_LC8_B13 = _LC8_B13~NOT;
_LC8_B13~NOT = LCELL( _EQ033);
_EQ033 = A4 & !_LC3_B13
# C8 & _LC8_B16;
-- Node name is '|mulx:41|mulx6:2|:128' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ034);
_EQ034 = !_LC2_B23
# !_LC7_B13
# !_LC8_B13;
Project Information d:\zhuhui\mycpu\xianshi\xianshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,954K
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