📄 xianshi.rpt
字号:
69 - - A -- OUTPUT 0 1 0 0 OUT5
54 - - - 21 OUTPUT 0 1 0 0 OUT6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhuhui\mycpu\xianshi\xianshi.rpt
xianshi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 21 OR2 0 2 1 0 |mulx:41|bcd7:1|A
- 8 - B 21 OR2 s 0 4 0 1 |mulx:41|bcd7:1|A~1
- 8 - B 17 OR2 0 3 1 0 |mulx:41|bcd7:1|B
- 2 - B 17 OR2 s 0 4 0 2 |mulx:41|bcd7:1|B~1
- 1 - B 17 OR2 0 4 1 0 |mulx:41|bcd7:1|C
- 4 - B 17 OR2 s 0 4 0 1 |mulx:41|bcd7:1|C~1
- 6 - B 17 OR2 s 0 4 0 1 |mulx:41|bcd7:1|C~2
- 3 - B 19 OR2 0 4 1 0 |mulx:41|bcd7:1|D
- 3 - B 21 OR2 0 4 1 0 |mulx:41|bcd7:1|E
- 5 - B 21 OR2 s 0 4 0 2 |mulx:41|bcd7:1|E~1
- 7 - B 21 OR2 s 0 4 0 1 |mulx:41|bcd7:1|E~2
- 7 - B 17 AND2 s 0 3 0 1 |mulx:41|bcd7:1|E~3
- 1 - B 21 OR2 0 4 1 0 |mulx:41|bcd7:1|F
- 5 - B 17 OR2 s 0 4 0 2 |mulx:41|bcd7:1|F~1
- 7 - B 19 OR2 0 4 1 0 |mulx:41|bcd7:1|G
- 3 - B 17 AND2 s 0 2 0 1 |mulx:41|bcd7:1|~57~1
- 2 - B 21 AND2 ! 0 4 0 2 |mulx:41|bcd7:1|:203
- 6 - B 21 AND2 ! 0 4 0 1 |mulx:41|bcd7:1|:232
- 8 - B 16 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~1
- 1 - B 16 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~2
- 7 - B 23 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~3
- 4 - B 23 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~4
- 8 - B 23 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~5
- 3 - B 13 DFFE + 0 1 1 5 |mulx:41|mulx6:2|SS~6
- 3 - B 23 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~122~1
- 4 - B 16 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~122~2
- 5 - B 16 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~122~3
- 2 - B 16 OR2 0 3 0 13 |mulx:41|mulx6:2|:122
- 5 - B 23 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~124~1
- 3 - B 16 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~124~2
- 6 - B 23 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~124~3
- 1 - B 23 AND2 ! 0 3 0 12 |mulx:41|mulx6:2|:124
- 4 - B 13 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~126~1
- 5 - B 13 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~126~2
- 6 - B 13 OR2 s 2 2 0 1 |mulx:41|mulx6:2|~126~3
- 2 - B 13 OR2 0 3 0 13 |mulx:41|mulx6:2|:126
- 2 - B 23 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~128~1
- 7 - B 13 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~128~2
- 8 - B 13 OR2 s ! 2 2 0 1 |mulx:41|mulx6:2|~128~3
- 1 - B 13 OR2 0 3 0 13 |mulx:41|mulx6:2|:128
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\zhuhui\mycpu\xianshi\xianshi.rpt
xianshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 14/ 96( 14%) 0/ 48( 0%) 20/ 48( 41%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhuhui\mycpu\xianshi\xianshi.rpt
xianshi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 STRUCK
Device-Specific Information: d:\zhuhui\mycpu\xianshi\xianshi.rpt
xianshi
** EQUATIONS **
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
A8 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
B8 : INPUT;
C1 : INPUT;
C2 : INPUT;
C3 : INPUT;
C4 : INPUT;
C5 : INPUT;
C6 : INPUT;
C7 : INPUT;
C8 : INPUT;
STRUCK : INPUT;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = !_LC3_B13;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC8_B23;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC4_B23;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC7_B23;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC1_B16;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC8_B16;
-- Node name is 'OUT0'
-- Equation name is 'OUT0', type is output
OUT0 = _LC7_B19;
-- Node name is 'OUT1'
-- Equation name is 'OUT1', type is output
OUT1 = _LC1_B21;
-- Node name is 'OUT2'
-- Equation name is 'OUT2', type is output
OUT2 = _LC3_B21;
-- Node name is 'OUT3'
-- Equation name is 'OUT3', type is output
OUT3 = _LC3_B19;
-- Node name is 'OUT4'
-- Equation name is 'OUT4', type is output
OUT4 = _LC1_B17;
-- Node name is 'OUT5'
-- Equation name is 'OUT5', type is output
OUT5 = _LC8_B17;
-- Node name is 'OUT6'
-- Equation name is 'OUT6', type is output
OUT6 = _LC4_B21;
-- Node name is '|mulx:41|bcd7:1|A' from file "bcd7.tdf" line 25, column 9
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ001);
_EQ001 = _LC8_B21
# _LC5_B21;
-- Node name is '|mulx:41|bcd7:1|A~1' from file "bcd7.tdf" line 25, column 9
-- Equation name is '_LC8_B21', type is buried
-- synthesized logic cell
_LC8_B21 = LCELL( _EQ002);
_EQ002 = !_LC1_B13 & _LC2_B13 & _LC2_B16
# !_LC1_B13 & _LC1_B23 & _LC2_B16
# _LC1_B13 & !_LC2_B13 & !_LC2_B16
# _LC1_B13 & !_LC1_B23 & !_LC2_B13
# _LC1_B23 & _LC2_B13 & _LC2_B16;
-- Node name is '|mulx:41|bcd7:1|B' from file "bcd7.tdf" line 23, column 11
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = LCELL( _EQ003);
_EQ003 = _LC7_B17
# _LC2_B17
# _LC5_B17;
-- Node name is '|mulx:41|bcd7:1|B~1' from file "bcd7.tdf" line 23, column 11
-- Equation name is '_LC2_B17', type is buried
-- synthesized logic cell
_LC2_B17 = LCELL( _EQ004);
_EQ004 = !_LC1_B13 & !_LC2_B13 & _LC2_B16
# !_LC1_B13 & _LC1_B23 & _LC2_B16
# _LC1_B13 & !_LC1_B23 & _LC2_B13 & _LC2_B16;
-- Node name is '|mulx:41|bcd7:1|C' from file "bcd7.tdf" line 23, column 13
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ005);
_EQ005 = _LC4_B17
# _LC5_B17
# _LC6_B17
# !_LC2_B21;
-- Node name is '|mulx:41|bcd7:1|C~1' from file "bcd7.tdf" line 23, column 13
-- Equation name is '_LC4_B17', type is buried
-- synthesized logic cell
_LC4_B17 = LCELL( _EQ006);
_EQ006 = _LC2_B17
# !_LC1_B23 & !_LC2_B16 & _LC3_B17;
-- Node name is '|mulx:41|bcd7:1|C~2' from file "bcd7.tdf" line 23, column 13
-- Equation name is '_LC6_B17', type is buried
-- synthesized logic cell
_LC6_B17 = LCELL( _EQ007);
_EQ007 = !_LC1_B13 & !_LC1_B23 & _LC2_B13 & _LC2_B16
# !_LC1_B13 & _LC1_B23 & _LC2_B13 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|D' from file "bcd7.tdf" line 24, column 15
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = LCELL( _EQ008);
_EQ008 = _LC1_B13 & !_LC1_B23 & !_LC2_B13
# !_LC1_B23 & !_LC2_B13 & !_LC2_B16
# !_LC1_B13 & _LC1_B23 & !_LC2_B13
# _LC1_B13 & _LC2_B13 & !_LC2_B16
# _LC1_B13 & !_LC1_B23 & !_LC2_B16
# !_LC1_B13 & _LC1_B23 & !_LC2_B16
# !_LC1_B23 & _LC2_B13 & _LC2_B16
# _LC1_B23 & !_LC2_B13 & _LC2_B16;
-- Node name is '|mulx:41|bcd7:1|E' from file "bcd7.tdf" line 25, column 17
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ009);
_EQ009 = _LC5_B21
# !_LC2_B21
# !_LC6_B21
# _LC7_B21;
-- Node name is '|mulx:41|bcd7:1|E~1' from file "bcd7.tdf" line 25, column 17
-- Equation name is '_LC5_B21', type is buried
-- synthesized logic cell
_LC5_B21 = LCELL( _EQ010);
_EQ010 = !_LC1_B13 & !_LC2_B13 & !_LC2_B16
# _LC1_B13 & _LC2_B13 & !_LC2_B16
# !_LC1_B13 & _LC1_B23 & !_LC2_B16;
-- Node name is '|mulx:41|bcd7:1|E~2' from file "bcd7.tdf" line 25, column 17
-- Equation name is '_LC7_B21', type is buried
-- synthesized logic cell
_LC7_B21 = LCELL( _EQ011);
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