📄 rom.rpt
字号:
- 3 - B 16 OR2 0 2 0 3 :768
- 8 - B 24 OR2 0 4 0 1 :837
- 3 - B 24 OR2 0 4 1 0 :846
- 2 - B 20 OR2 2 2 0 2 :858
- 6 - B 16 OR2 0 4 0 1 :872
- 7 - B 16 OR2 0 4 0 1 :876
- 1 - B 16 OR2 0 4 0 1 :953
- 4 - B 24 OR2 0 4 1 0 :957
- 4 - B 16 OR2 0 2 0 1 :978
- 2 - B 17 OR2 0 4 0 1 :984
- 3 - B 11 OR2 0 3 0 1 :990
- 6 - B 11 OR2 0 4 0 1 :1034
- 4 - B 03 OR2 s ! 0 2 0 4 ~1058~1
- 7 - B 11 OR2 0 4 0 1 :1059
- 8 - B 11 OR2 0 4 1 0 :1070
- 4 - B 22 OR2 2 2 0 3 :1197
- 1 - B 17 OR2 0 3 0 1 :1203
- 2 - B 11 OR2 0 3 0 1 :1209
- 5 - B 11 OR2 0 4 0 1 :1254
- 4 - B 01 OR2 s ! 0 2 0 2 ~1286~1
- 3 - B 01 OR2 0 4 1 0 :1292
- 1 - B 24 AND2 s ! 0 3 0 1 ~1398~1
- 4 - B 20 OR2 s 0 4 0 1 ~1398~2
- 1 - B 20 OR2 0 3 1 0 :1403
- 6 - B 03 AND2 ! 0 2 0 4 :1497
- 2 - B 24 AND2 s 0 2 0 7 ~1514~1
- 7 - B 01 AND2 s 0 3 0 6 ~1514~2
- 3 - B 03 OR2 0 3 1 0 :1514
- 2 - B 07 OR2 s ! 0 2 0 4 ~1736~1
- 4 - B 07 OR2 0 4 1 0 :1736
- 2 - B 12 OR2 0 2 0 3 :1899
- 2 - B 04 OR2 s ! 0 2 0 6 ~1958~1
- 1 - B 12 AND2 0 4 1 0 :1958
- 8 - B 10 OR2 s 0 3 0 1 ~2018~1
- 1 - B 10 OR2 0 4 1 0 :2069
- 8 - B 12 OR2 0 3 1 0 :2180
- 8 - B 16 OR2 s 0 2 0 3 ~2211~1
- 3 - B 17 OR2 s 0 2 0 1 ~2211~2
- 5 - B 16 OR2 s 0 4 0 2 ~2211~3
- 2 - B 16 OR2 0 4 0 1 :2219
- 7 - B 04 OR2 0 4 0 1 :2223
- 8 - B 04 OR2 0 4 0 1 :2237
- 5 - B 04 OR2 0 4 1 0 :2289
- 4 - B 02 OR2 0 4 0 1 :2331
- 6 - B 02 OR2 0 4 0 1 :2345
- 7 - B 02 OR2 0 4 0 1 :2349
- 8 - B 02 OR2 0 4 0 1 :2361
- 1 - B 01 AND2 s 0 2 0 4 ~2402~1
- 5 - B 02 AND2 0 4 1 0 :2402
- 1 - B 02 OR2 s 0 3 0 2 ~2436~1
- 5 - B 05 OR2 0 3 0 1 :2444
- 6 - B 05 OR2 0 3 0 1 :2450
- 8 - B 05 OR2 0 4 0 1 :2454
- 3 - B 05 OR2 0 4 0 1 :2471
- 5 - B 09 AND2 s ! 0 2 0 1 ~2481~1
- 1 - B 03 OR2 0 4 1 0 :2511
- 3 - B 04 OR2 0 4 0 1 :2562
- 4 - B 04 OR2 0 4 0 2 :2576
- 1 - B 11 OR2 s ! 0 3 0 4 ~2624~1
- 6 - B 04 OR2 s 0 4 1 0 ~2624~2
- 1 - B 04 OR2 0 4 1 0 :2624
- 8 - B 03 OR2 s 0 4 0 1 ~3395~1
- 5 - B 03 OR2 0 4 1 0 :3401
- 3 - B 02 OR2 0 4 0 2 :3446
- 5 - B 12 OR2 0 4 0 1 :3450
- 7 - B 12 OR2 0 4 0 1 :3464
- 2 - B 01 OR2 0 4 0 1 :3468
- 7 - B 03 AND2 s ! 0 2 0 3 ~3501~1
- 6 - B 01 OR2 0 4 0 1 :3501
- 5 - B 01 AND2 0 3 1 0 :3512
- 4 - B 17 OR2 0 2 0 2 :3525
- 8 - B 17 OR2 0 4 0 2 :3539
- 6 - B 09 OR2 0 4 0 1 :3543
- 8 - B 09 OR2 0 4 0 1 :3557
- 4 - B 10 OR2 0 4 0 1 :3561
- 1 - B 07 AND2 s 0 2 0 2 ~3596~1
- 2 - B 03 AND2 s 0 2 0 3 ~3596~2
- 6 - B 10 AND2 s 0 2 0 2 ~3596~3
- 7 - B 10 AND2 0 4 0 1 :3596
- 7 - B 23 OR2 s ! 2 2 0 2 ~3600~1
- 4 - B 23 AND2 s ! 0 2 0 4 ~3600~2
- 6 - B 15 AND2 s 0 2 0 5 ~3623~1
- 5 - B 10 OR2 0 4 1 0 :3623
- 6 - B 12 OR2 s ! 0 2 0 2 ~3680~1
- 4 - B 12 AND2 0 4 0 1 :3680
- 3 - B 12 OR2 0 4 0 1 :3684
- 2 - B 10 OR2 0 4 0 1 :3705
- 3 - B 10 OR2 0 4 1 0 :3734
- 3 - B 09 OR2 0 4 0 1 :3777
- 1 - B 09 AND2 s 0 4 0 1 ~3779~1
- 4 - B 09 OR2 0 4 0 1 :3803
- 2 - B 09 OR2 0 4 0 1 :3810
- 6 - B 23 OR2 0 4 0 1 :3819
- 1 - B 15 OR2 0 4 0 1 :3833
- 6 - B 24 OR2 0 4 0 1 :3842
- 7 - B 24 OR2 0 3 1 0 :3845
- 5 - B 17 OR2 0 4 0 1 :3861
- 7 - B 17 OR2 0 4 0 1 :3881
- 1 - B 05 OR2 s 0 4 0 1 ~3921~1
- 4 - B 05 OR2 s 0 4 0 2 ~3921~2
- 4 - B 11 OR2 s 0 3 0 2 ~3921~3
- 6 - B 17 OR2 0 4 1 0 :3954
- 5 - B 24 AND2 s 0 3 0 1 ~3956~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\rom.rpt
rom
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 50/ 96( 52%) 22/ 48( 45%) 14/ 48( 29%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\rom.rpt
rom
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC7_B5;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC8_B20;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC3_B24;
-- Node name is 'D4'
-- Equation name is 'D4', type is output
D4 = _LC4_B24;
-- Node name is 'D5'
-- Equation name is 'D5', type is output
D5 = _LC8_B11;
-- Node name is 'D6'
-- Equation name is 'D6', type is output
D6 = _LC1_B14;
-- Node name is 'D7'
-- Equation name is 'D7', type is output
D7 = _LC3_B1;
-- Node name is 'D8'
-- Equation name is 'D8', type is output
D8 = _LC1_B20;
-- Node name is 'D9'
-- Equation name is 'D9', type is output
D9 = _LC3_B3;
-- Node name is 'D10'
-- Equation name is 'D10', type is output
D10 = GND;
-- Node name is 'D11'
-- Equation name is 'D11', type is output
D11 = _LC4_B7;
-- Node name is 'D12'
-- Equation name is 'D12', type is output
D12 = _LC8_B6;
-- Node name is 'D13'
-- Equation name is 'D13', type is output
D13 = _LC1_B12;
-- Node name is 'D14'
-- Equation name is 'D14', type is output
D14 = _LC1_B10;
-- Node name is 'D15'
-- Equation name is 'D15', type is output
D15 = _LC8_B12;
-- Node name is 'D16'
-- Equation name is 'D16', type is output
D16 = _LC5_B4;
-- Node name is 'D17'
-- Equation name is 'D17', type is output
D17 = _LC5_B2;
-- Node name is 'D18'
-- Equation name is 'D18', type is output
D18 = _LC1_B3;
-- Node name is 'D19'
-- Equation name is 'D19', type is output
D19 = _LC6_B4;
-- Node name is 'D20'
-- Equation name is 'D20', type is output
D20 = _LC1_B4;
-- Node name is 'D21'
-- Equation name is 'D21', type is output
D21 = _LC2_B21;
-- Node name is 'D22'
-- Equation name is 'D22', type is output
D22 = _LC7_B21;
-- Node name is 'D23'
-- Equation name is 'D23', type is output
D23 = _LC5_B21;
-- Node name is 'D24'
-- Equation name is 'D24', type is output
D24 = _LC2_B8;
-- Node name is 'D25'
-- Equation name is 'D25', type is output
D25 = _LC4_B6;
-- Node name is 'D26'
-- Equation name is 'D26', type is output
D26 = _LC5_B3;
-- Node name is 'D27'
-- Equation name is 'D27', type is output
D27 = _LC5_B1;
-- Node name is 'D28'
-- Equation name is 'D28', type is output
D28 = _LC5_B10;
-- Node name is 'D29'
-- Equation name is 'D29', type is output
D29 = _LC3_B10;
-- Node name is 'D30'
-- Equation name is 'D30', type is output
D30 = _LC7_B24;
-- Node name is 'D31'
-- Equation name is 'D31', type is output
D31 = _LC6_B17;
-- Node name is ':146'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ001);
_EQ001 = !A3 & !A4 & !A5 & _LC6_B6;
-- Node name is ':153'
-- Equation name is '_LC5_B15', type is buried
!_LC5_B15 = _LC5_B15~NOT;
_LC5_B15~NOT = LCELL( _EQ002);
_EQ002 = A3
# A4
# !_LC4_B14
# A5;
-- Node name is '~160~1'
-- Equation name is '~160~1', location is LC2_B21, type is buried.
-- synthesized logic cell
_LC2_B21 = LCELL( _EQ003);
_EQ003 = !A0 & !A2 & !A5 & _LC3_B21;
-- Node name is ':160'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ004);
_EQ004 = !A0 & !A2 & !A5 & _LC3_B21;
-- Node name is ':167'
-- Equation name is '_LC3_B8', type is buried
!_LC3_B8 = _LC3_B8~NOT;
_LC3_B8~NOT = LCELL( _EQ005);
_EQ005 = !_LC6_B6
# A3
# A4
# !A5;
-- Node name is ':174'
-- Equation name is '_LC8_B22', type is buried
!_LC8_B22 = _LC8_B22~NOT;
_LC8_B22~NOT = LCELL( _EQ006);
_EQ006 = !A5
# !_LC4_B14
# A3
# A4;
-- Node name is ':181'
-- Equation name is '_LC1_B21', type is buried
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL( _EQ007);
_EQ007 = A2
# A0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -