📄 bumaqi.rpt
字号:
18 - - A -- INPUT 0 0 0 2 A2
16 - - A -- INPUT 0 0 0 3 A3
19 - - A -- INPUT 0 0 0 2 A4
48 - - - 15 INPUT 0 0 0 2 A5
81 - - - 22 INPUT 0 0 0 1 A6
84 - - - -- INPUT 0 0 0 7 A7
44 - - - -- INPUT 0 0 0 16 B0
17 - - A -- INPUT 0 0 0 5 B1
51 - - - 18 INPUT 0 0 0 2 B2
1 - - - -- INPUT 0 0 0 6 B3
69 - - A -- INPUT 0 0 0 2 B4
49 - - - 16 INPUT 0 0 0 3 B5
43 - - - -- INPUT 0 0 0 1 B6
42 - - - -- INPUT 0 0 0 13 B7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\multi\cpu\bumaqi.rpt
bumaqi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - 24 OUTPUT 0 1 0 0 M0
80 - - - 23 OUTPUT 0 1 0 0 M1
79 - - - 24 OUTPUT 0 1 0 0 M2
70 - - A -- OUTPUT 0 1 0 0 M3
73 - - A -- OUTPUT 0 1 0 0 M4
72 - - A -- OUTPUT 0 1 0 0 M5
54 - - - 21 OUTPUT 0 1 0 0 M6
71 - - A -- OUTPUT 0 1 0 0 M7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\multi\cpu\bumaqi.rpt
bumaqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 19 OR2 3 0 0 9 |buyuanyima:2|74157:26|Y2 (|buyuanyima:2|74157:26|:23)
- 3 - A 19 OR2 4 0 0 8 |buyuanyima:2|74157:26|Y3 (|buyuanyima:2|74157:26|:24)
- 2 - A 19 OR2 2 1 0 7 |buyuanyima:2|74157:26|Y4 (|buyuanyima:2|74157:26|:25)
- 6 - A 19 OR2 3 1 0 5 |buyuanyima:2|74157:27|Y1 (|buyuanyima:2|74157:27|:22)
- 5 - A 14 OR2 2 1 0 3 |buyuanyima:2|74157:27|Y2 (|buyuanyima:2|74157:27|:23)
- 6 - A 14 OR2 3 1 0 1 |buyuanyima:2|74157:27|Y3 (|buyuanyima:2|74157:27|:24)
- 8 - A 19 AND2 3 0 0 3 |buyuanyima:2|74183:2|:13
- 7 - A 19 AND2 2 1 0 2 |buyuanyima:2|74183:7|:13
- 2 - A 18 OR2 3 0 0 7 |buyuanyima:3|74157:26|Y2 (|buyuanyima:3|74157:26|:23)
- 4 - A 18 OR2 4 0 0 9 |buyuanyima:3|74157:26|Y3 (|buyuanyima:3|74157:26|:24)
- 6 - A 13 OR2 3 1 0 4 |buyuanyima:3|74157:27|Y1 (|buyuanyima:3|74157:27|:22)
- 3 - A 13 OR2 3 1 0 1 |buyuanyima:3|74157:27|Y3 (|buyuanyima:3|74157:27|:24)
- 1 - A 18 AND2 3 0 0 6 |buyuanyima:3|74183:2|:13
- 8 - A 13 AND2 2 1 0 3 |buyuanyima:3|74183:7|:13
- 8 - A 20 AND2 s 1 2 0 1 B0~1
- 3 - A 20 AND2 s 1 3 0 2 B0~2
- 8 - A 24 AND2 s 1 3 0 1 B0~3
- 7 - A 18 AND2 0 2 0 2 |MULTI:75|one_bit_adder:U_0_0|:12
- 3 - A 18 OR2 1 3 0 2 |MULTI:75|one_bit_adder:U_0_1|:8
- 6 - A 20 OR2 1 3 0 2 |MULTI:75|one_bit_adder:U_0_1|:15
- 1 - A 20 OR2 0 2 0 2 |MULTI:75|one_bit_adder:U_0_2|:8
- 4 - A 20 OR2 1 3 0 2 |MULTI:75|one_bit_adder:U_0_2|:13
- 7 - A 20 OR2 0 4 0 3 |MULTI:75|one_bit_adder:U_0_2|:15
- 5 - A 20 OR2 0 2 0 2 |MULTI:75|one_bit_adder:U_0_3|:8
- 2 - A 20 OR2 1 3 0 3 |MULTI:75|one_bit_adder:U_0_3|:13
- 2 - A 24 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_0_4|:8
- 6 - A 24 OR2 1 3 0 2 |MULTI:75|one_bit_adder:U_0_4|:13
- 7 - A 24 OR2 0 4 0 1 |MULTI:75|one_bit_adder:U_0_4|:14
- 6 - A 23 OR2 1 2 0 3 |MULTI:75|one_bit_adder:U_1_0|:7
- 5 - A 16 AND2 1 2 0 2 |MULTI:75|one_bit_adder:U_1_0|:12
- 4 - A 16 OR2 0 4 0 5 |MULTI:75|one_bit_adder:U_1_1|:8
- 6 - A 16 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_1_1|:15
- 8 - A 16 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_1_2|:8
- 3 - A 16 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_1_2|:15
- 1 - A 19 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_1_3|:8
- 4 - A 19 OR2 0 4 0 1 |MULTI:75|one_bit_adder:U_1_3|:15
- 7 - A 16 AND2 0 2 0 1 |MULTI:75|one_bit_adder:U_2_0|:12
- 2 - A 16 OR2 0 4 0 4 |MULTI:75|one_bit_adder:U_2_1|:8
- 1 - A 16 OR2 0 4 0 2 |MULTI:75|one_bit_adder:U_2_1|:15
- 1 - A 21 OR2 0 3 0 2 |MULTI:75|one_bit_adder:U_2_2|:8
- 6 - A 15 AND2 0 2 0 2 |MULTI:75|one_bit_adder:U_3_0|:12
- 3 - A 15 OR2 0 4 0 3 |MULTI:75|one_bit_adder:U_3_1|:8
- 4 - A 15 OR2 0 4 0 1 |MULTI:75|one_bit_adder:U_3_1|:15
- 7 - A 21 OR2 0 2 0 1 |MULTI:75|one_bit_adder:U_4_0|:7
- 3 - A 24 OR2 s 0 4 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~1
- 8 - A 15 OR2 s 0 4 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~2
- 4 - A 24 OR2 s 1 2 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~3
- 5 - A 24 OR2 s 1 3 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~4
- 1 - A 24 OR2 s 0 4 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~5
- 5 - A 21 OR2 s 0 4 0 1 |MULTI:75|one_bit_adder:U_5_0|~7~6
- 6 - A 21 OR2 0 4 0 1 |MULTI:75|one_bit_adder:U_5_0|:7
- 7 - A 23 AND2 2 0 1 2 |MULTI:75|:2088
- 6 - A 18 AND2 1 1 0 3 |MULTI:75|:2105
- 5 - A 18 OR2 4 0 0 3 |MULTI:75|:2308
- 8 - A 18 OR2 3 1 0 2 |MULTI:75|:2325
- 1 - A 13 OR2 3 1 0 5 |MULTI:75|:2686
- 7 - A 13 OR2 2 2 0 2 |MULTI:75|:2703
- 4 - A 21 OR2 2 2 0 2 |MULTI:75|:2720
- 4 - A 13 OR2 2 2 0 1 |MULTI:75|:2737
- 5 - A 15 AND2 1 1 0 4 |MULTI:75|:2875
- 2 - A 13 OR2 3 1 0 3 |MULTI:75|:3064
- 5 - A 13 OR2 2 2 0 1 |MULTI:75|:3081
- 8 - A 23 OR2 s 0 4 0 1 |yuanbuyima:47|74157:24|~21~1
- 3 - A 23 OR2 0 4 1 0 |yuanbuyima:47|74157:24|Y2 (|yuanbuyima:47|74157:24|:23)
- 4 - A 23 OR2 0 3 1 0 |yuanbuyima:47|74157:24|Y3 (|yuanbuyima:47|74157:24|:24)
- 5 - A 23 OR2 0 4 1 0 |yuanbuyima:47|74157:24|Y4 (|yuanbuyima:47|74157:24|:25)
- 7 - A 15 OR2 s 0 3 0 1 |yuanbuyima:47|74157:25|~15~1
- 1 - A 15 OR2 0 4 1 0 |yuanbuyima:47|74157:25|Y1 (|yuanbuyima:47|74157:25|:22)
- 3 - A 21 OR2 0 4 1 0 |yuanbuyima:47|74157:25|Y2 (|yuanbuyima:47|74157:25|:23)
- 2 - A 21 OR2 0 4 1 0 |yuanbuyima:47|74157:25|Y3 (|yuanbuyima:47|74157:25|:24)
- 2 - A 23 OR2 0 3 0 3 |yuanbuyima:47|74183:2|:31
- 1 - A 23 OR2 0 4 0 2 |yuanbuyima:47|74183:3|:31
- 2 - A 15 OR2 0 3 0 2 |yuanbuyima:47|74183:4|:12
- 4 - A 14 OR2 2 0 1 6 :46
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\bumaqi.rpt
bumaqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 20/ 96( 20%) 0/ 48( 0%) 35/ 48( 72%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\bumaqi.rpt
bumaqi
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
-- Node name is 'B0~1'
-- Equation name is 'B0~1', location is LC8_A20, type is buried.
-- synthesized logic cell
_LC8_A20 = LCELL( _EQ001);
_EQ001 = B0 & _LC2_A18 & _LC2_A19;
-- Node name is 'B0~2'
-- Equation name is 'B0~2', location is LC3_A20, type is buried.
-- synthesized logic cell
_LC3_A20 = LCELL( _EQ002);
_EQ002 = B0 & _LC2_A18 & _LC2_A19 & _LC6_A19;
-- Node name is 'B0~3'
-- Equation name is 'B0~3', location is LC8_A24, type is buried.
-- synthesized logic cell
_LC8_A24 = LCELL( _EQ003);
_EQ003 = B0 & _LC2_A18 & _LC5_A14 & _LC6_A19;
-- Node name is 'M0'
-- Equation name is 'M0', type is output
M0 = _LC7_A23;
-- Node name is 'M1'
-- Equation name is 'M1', type is output
M1 = _LC3_A23;
-- Node name is 'M2'
-- Equation name is 'M2', type is output
M2 = _LC4_A23;
-- Node name is 'M3'
-- Equation name is 'M3', type is output
M3 = _LC5_A23;
-- Node name is 'M4'
-- Equation name is 'M4', type is output
M4 = _LC1_A15;
-- Node name is 'M5'
-- Equation name is 'M5', type is output
M5 = _LC3_A21;
-- Node name is 'M6'
-- Equation name is 'M6', type is output
M6 = _LC2_A21;
-- Node name is 'M7'
-- Equation name is 'M7', type is output
M7 = _LC4_A14;
-- Node name is '|buyuanyima:2|74157:26|:23' = '|buyuanyima:2|74157:26|Y2'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ004);
_EQ004 = A0 & !A1 & A7
# !A0 & A1
# A1 & !A7;
-- Node name is '|buyuanyima:2|74157:26|:24' = '|buyuanyima:2|74157:26|Y3'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ005);
_EQ005 = !A0 & !A1 & A2
# A1 & !A2 & A7
# A0 & !A2 & A7
# A2 & !A7;
-- Node name is '|buyuanyima:2|74157:26|:25' = '|buyuanyima:2|74157:26|Y4'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ006);
_EQ006 = A3 & _LC8_A19
# !A3 & A7 & !_LC8_A19
# A3 & !A7;
-- Node name is '|buyuanyima:2|74157:27|:22' = '|buyuanyima:2|74157:27|Y1'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = LCELL( _EQ007);
_EQ007 = !A3 & A4 & _LC8_A19
# !A4 & A7 & !_LC8_A19
# A3 & !A4 & A7
# A4 & !A7;
-- Node name is '|buyuanyima:2|74157:27|:23' = '|buyuanyima:2|74157:27|Y2'
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