📄 buyuanyima.rpt
字号:
- 8 - B 06 OR2 3 1 1 0 |74157:27|Y2 (|74157:27|:23)
- 1 - B 06 OR2 3 1 1 0 |74157:27|Y3 (|74157:27|:24)
- 2 - B 06 AND2 3 0 0 4 |74183:2|:13
- 7 - B 06 OR2 ! 1 1 0 1 |74183:2|:32
- 5 - B 06 AND2 2 1 0 2 |74183:7|:13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\buyuanyima.rpt
buyuanyima
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
C: 2/ 96( 2%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\buyuanyima.rpt
buyuanyima
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
-- Node name is 'O0~1'
-- Equation name is 'O0~1', location is LC1_C1, type is buried.
-- synthesized logic cell
_LC1_C1 = LCELL( D0);
-- Node name is 'O0'
-- Equation name is 'O0', type is output
O0 = _LC1_C1;
-- Node name is 'O1'
-- Equation name is 'O1', type is output
O1 = _LC5_C1;
-- Node name is 'O2'
-- Equation name is 'O2', type is output
O2 = _LC3_C1;
-- Node name is 'O3'
-- Equation name is 'O3', type is output
O3 = _LC6_B6;
-- Node name is 'O4'
-- Equation name is 'O4', type is output
O4 = _LC3_B6;
-- Node name is 'O5'
-- Equation name is 'O5', type is output
O5 = _LC8_B6;
-- Node name is 'O6'
-- Equation name is 'O6', type is output
O6 = _LC1_B6;
-- Node name is 'O7'
-- Equation name is 'O7', type is output
O7 = _LC4_B6;
-- Node name is '|74157:26|:23' = '|74157:26|Y2'
-- Equation name is '_LC5_C1', type is buried
_LC5_C1 = LCELL( _EQ001);
_EQ001 = !D0 & D1
# D0 & !D1 & D7
# D1 & !D7;
-- Node name is '|74157:26|:24' = '|74157:26|Y3'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ002);
_EQ002 = !D0 & !D1 & D2
# D1 & !D2 & D7
# D0 & !D2 & D7
# D2 & !D7;
-- Node name is '|74157:26|:25' = '|74157:26|Y4'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ003);
_EQ003 = D3 & _LC2_B6
# !D3 & D7 & !_LC2_B6
# D3 & !D7;
-- Node name is '|74157:27|:22' = '|74157:27|Y1'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ004);
_EQ004 = !D4 & D7 & !_LC2_B6
# D3 & !D4 & D7
# !D3 & D4 & _LC2_B6
# D4 & !D7;
-- Node name is '|74157:27|:23' = '|74157:27|Y2'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = LCELL( _EQ005);
_EQ005 = !D5 & D7 & !_LC7_B6
# D4 & !D5 & D7
# !D4 & D5 & _LC7_B6
# D5 & !D7;
-- Node name is '|74157:27|:24' = '|74157:27|Y3'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ006);
_EQ006 = D5 & !D6 & D7
# !D6 & D7 & !_LC5_B6
# !D5 & D6 & _LC5_B6
# D6 & !D7;
-- Node name is '|74157:27|:20'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ007);
_EQ007 = !D5 & !D6 & D7 & _LC5_B6;
-- Node name is '|74183:2|:13'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ008);
_EQ008 = !D0 & !D1 & !D2;
-- Node name is '|74183:2|:32'
-- Equation name is '_LC7_B6', type is buried
!_LC7_B6 = _LC7_B6~NOT;
_LC7_B6~NOT = LCELL( _EQ009);
_EQ009 = !_LC2_B6
# D3;
-- Node name is '|74183:7|:13'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ010);
_EQ010 = !D3 & !D4 & _LC2_B6;
Project Information c:\maxplus2\multi\cpu\buyuanyima.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,421K
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