📄 yunsuan33.rpt
字号:
80 - - - 23 INPUT 0 0 0 1 N5
27 - - C -- INPUT 0 0 0 1 N6
60 - - C -- INPUT 0 0 0 1 N7
19 - - A -- INPUT 0 0 0 4 RI-BUS
71 - - A -- INPUT 0 0 0 2 SELRI
21 - - B -- INPUT 0 0 0 1 SIGNAL
1 - - - -- INPUT 0 0 0 8 SW-BUS
38 - - - 10 INPUT 0 0 0 8 S0
43 - - - -- INPUT 0 0 0 8 S1
44 - - - -- INPUT 0 0 0 8 S2
84 - - - -- INPUT 0 0 0 8 S3
50 - - - 17 INPUT 0 0 0 6 T2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\yunsuan33.rpt
yunsuan33
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
62 - - C -- OUTPUT 0 1 0 0 BUS0
66 - - B -- OUTPUT 0 1 0 0 BUS1
58 - - C -- OUTPUT 0 1 0 0 BUS2
59 - - C -- OUTPUT 0 1 0 0 BUS3
29 - - C -- OUTPUT 0 1 0 0 BUS4
28 - - C -- OUTPUT 0 1 0 0 BUS5
30 - - C -- OUTPUT 0 1 0 0 BUS6
64 - - B -- OUTPUT 0 1 0 0 BUS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\yunsuan33.rpt
yunsuan33
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 14 OR2 0 4 0 1 |MULTI:7|one_bit_adder:U_0_0|:7
- 3 - C 03 AND2 0 4 0 3 |MULTI:7|one_bit_adder:U_0_0|:12
- 1 - C 03 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_1|:8
- 4 - C 03 AND2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_1|:12
- 6 - C 03 OR2 0 3 0 1 |MULTI:7|one_bit_adder:U_0_1|:15
- 7 - C 03 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_2|:8
- 4 - C 12 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_2|:13
- 2 - C 12 OR2 0 3 0 4 |MULTI:7|one_bit_adder:U_0_2|:15
- 7 - C 01 OR2 0 4 0 4 |MULTI:7|one_bit_adder:U_0_3|:13
- 2 - C 01 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_4|:8
- 4 - C 01 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_0_4|:13
- 6 - C 01 OR2 0 4 0 1 |MULTI:7|one_bit_adder:U_0_4|:14
- 8 - C 03 AND2 0 3 0 2 |MULTI:7|one_bit_adder:U_1_0|:12
- 2 - C 03 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_1_1|:8
- 5 - C 03 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_1_1|:15
- 8 - C 01 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_1_2|:8
- 1 - C 01 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_1_2|:15
- 8 - C 10 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_1_3|:8
- 4 - C 10 OR2 0 4 0 1 |MULTI:7|one_bit_adder:U_1_3|:15
- 5 - C 02 AND2 0 3 0 2 |MULTI:7|one_bit_adder:U_2_0|:12
- 7 - C 02 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_2_1|:8
- 1 - C 02 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_2_1|:15
- 6 - C 02 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_2_2|:8
- 5 - C 10 OR2 0 4 0 1 |MULTI:7|one_bit_adder:U_2_2|:15
- 8 - C 02 AND2 0 3 0 2 |MULTI:7|one_bit_adder:U_3_0|:12
- 2 - C 02 OR2 0 4 0 2 |MULTI:7|one_bit_adder:U_3_1|:8
- 3 - C 02 OR2 0 4 0 1 |MULTI:7|one_bit_adder:U_3_1|:15
- 3 - C 12 OR2 s 0 4 0 1 |MULTI:7|one_bit_adder:U_4_1|~8~1
- 1 - C 10 OR2 s 0 4 0 1 |MULTI:7|one_bit_adder:U_4_1|~8~2
- 3 - C 10 OR2 s 0 4 0 1 |MULTI:7|one_bit_adder:U_4_1|~8~3
- 6 - C 10 OR2 s 0 4 0 1 |MULTI:7|one_bit_adder:U_4_1|~8~4
- 1 - C 11 OR2 s 0 4 0 1 |MULTI:7|one_bit_adder:U_4_1|~8~5
- 8 - C 12 AND2 0 2 0 1 |MULTI:7|:1401
- 7 - C 09 AND2 0 2 0 2 |MULTI:7|:1716
- 4 - C 16 AND2 0 2 0 1 |MULTI:7|:1830
- 2 - A 15 OR2 3 0 0 8 |risel:1|2sel1:17|Y1 (|risel:1|2sel1:17|:101)
- 1 - A 15 OR2 ! 3 0 0 8 |risel:1|2sel1:17|Y2 (|risel:1|2sel1:17|:102)
- 4 - A 14 AND2 2 2 0 8 |risel:1|R1LD (|risel:1|:8)
- 3 - A 14 AND2 2 2 0 8 |risel:1|R2LD (|risel:1|:9)
- 2 - A 14 AND2 2 2 0 8 |risel:1|R3LD (|risel:1|:10)
- 1 - A 14 AND2 2 2 0 8 |risel:1|R4LD (|risel:1|:11)
- 7 - A 14 OR2 ! 1 2 0 8 |risel:1|:19
- 6 - A 14 OR2 ! 1 2 0 8 |risel:1|:20
- 5 - A 14 OR2 ! 1 2 0 8 |risel:1|:21
- 8 - A 14 OR2 ! 1 2 0 8 |risel:1|:22
- 4 - B 10 AND2 2 0 0 8 :18
- 1 - B 08 AND2 2 0 0 8 :19
- 2 - C 05 OR2 ! 2 2 0 3 |74181:20|:43
- 1 - C 04 OR2 ! 2 2 0 2 |74181:20|:44
- 3 - C 06 OR2 2 2 0 2 |74181:20|:45
- 5 - C 05 OR2 ! 2 2 0 2 |74181:20|:46
- 3 - C 04 OR2 ! 2 2 0 2 |74181:20|:47
- 2 - C 06 OR2 2 2 0 2 |74181:20|:48
- 1 - B 12 OR2 s 2 1 0 1 |74181:20|~51~1
- 3 - B 12 OR2 s 2 1 0 1 |74181:20|~52~1
- 6 - C 05 OR2 1 3 0 1 |74181:20|:64
- 7 - C 05 OR2 s 0 4 0 2 |74181:20|~73~1
- 6 - C 04 OR2 s 0 4 0 2 |74181:20|~74~1
- 1 - C 06 OR2 1 3 0 1 |74181:20|:74
- 2 - B 12 OR2 0 4 0 1 |74181:20|:77
- 5 - C 04 OR2 1 2 0 1 |74181:20|:79
- 5 - C 06 OR2 1 3 0 1 |74181:20|:82
- 6 - C 12 OR2 ! 2 2 0 2 |74181:21|:43
- 5 - C 12 OR2 ! 2 2 0 3 |74181:21|:44
- 7 - C 12 OR2 ! 2 2 0 2 |74181:21|:45
- 3 - C 09 OR2 ! 2 2 0 2 |74181:21|:46
- 4 - C 07 OR2 ! 2 2 0 3 |74181:21|:47
- 6 - C 09 OR2 ! 2 2 0 2 |74181:21|:48
- 3 - C 05 OR2 ! 2 2 0 3 |74181:21|:51
- 4 - C 05 OR2 ! 2 2 0 3 |74181:21|:52
- 8 - C 07 OR2 1 3 0 1 |74181:21|:75
- 8 - C 05 OR2 1 3 0 1 |74181:21|:77
- 6 - C 07 OR2 s 1 2 0 3 |74181:21|CN4~1 (|74181:21|~78~1)
- 7 - C 07 OR2 s 0 2 0 1 |74181:21|CN4~2 (|74181:21|~78~2)
- 1 - C 07 OR2 s 0 4 0 3 |74181:21|CN4~3 (|74181:21|~78~3)
- 3 - C 07 OR2 2 2 0 1 |74181:21|:80
- 2 - C 07 OR2 1 3 0 1 |74181:21|:81
- 3 - C 18 OR2 s 1 3 0 1 |74244:28|~1~1~1
- 5 - C 14 OR2 2 2 0 1 |74244:28|~6~1
- 6 - C 16 OR2 s 1 3 0 1 |74244:28|~11~1~1
- 2 - B 14 OR2 3 1 0 1 |74244:28|~26~1
- 2 - C 11 OR2 s 1 3 0 1 |74244:28|~27~1~1
- 4 - C 23 OR2 s 0 4 0 1 |74244:30|~1~1~1~2
- 2 - C 18 OR2 s 0 3 0 1 |74244:30|~1~1~1~3
- 4 - C 18 OR2 s 3 1 0 1 |74244:30|~1~1~1~4
- 1 - C 18 OR2 0 4 1 6 |74244:30|~1~1~1
- 1 - C 14 OR2 s 0 4 0 1 |74244:30|~6~1~1~2
- 4 - C 17 OR2 s 2 2 0 1 |74244:30|~6~1~1~3
- 3 - C 14 OR2 s 0 3 0 1 |74244:30|~6~1~1~4
- 2 - C 14 AND2 0 3 1 6 |74244:30|~6~1~1
- 1 - C 21 OR2 s 0 4 0 1 |74244:30|~10~1~1~2
- 8 - C 17 OR2 s 2 2 0 1 |74244:30|~10~1~1~3
- 2 - C 22 OR2 s 0 4 0 1 |74244:30|~10~1~1~4
- 6 - C 22 OR2 1 3 1 6 |74244:30|~10~1~1
- 1 - C 16 OR2 s 0 4 0 1 |74244:30|~11~1~1~2
- 2 - C 16 OR2 s 2 2 0 1 |74244:30|~11~1~1~3
- 3 - C 16 OR2 s 0 3 0 1 |74244:30|~11~1~1~4
- 5 - C 16 OR2 1 3 1 6 |74244:30|~11~1~1
- 1 - B 14 OR2 s 0 4 0 1 |74244:30|~26~1~1~2
- 2 - C 17 OR2 s 2 2 0 1 |74244:30|~26~1~1~3
- 1 - B 18 OR2 s 0 3 0 1 |74244:30|~26~1~1~4
- 7 - B 14 AND2 0 3 1 6 |74244:30|~26~1~1
- 2 - C 21 OR2 s 2 2 0 1 |74244:30|~27~1~1~2
- 3 - C 21 OR2 s 0 3 0 1 |74244:30|~27~1~1~3
- 4 - C 21 OR2 s 0 4 0 1 |74244:30|~27~1~1~4
- 7 - C 21 OR2 1 3 1 6 |74244:30|~27~1~1
- 2 - C 20 OR2 s 0 4 0 1 |74244:30|~31~1~1~2
- 4 - C 19 OR2 s 2 2 0 1 |74244:30|~31~1~1~3
- 4 - C 04 OR2 s 0 4 0 1 |74244:30|~31~1~1~4
- 2 - C 04 OR2 1 3 1 6 |74244:30|~31~1~1
- 8 - C 20 OR2 s 0 4 0 1 |74244:30|~36~1~1~2
- 2 - C 23 OR2 s 2 2 0 1 |74244:30|~36~1~1~3
- 1 - C 15 OR2 s 0 4 0 1 |74244:30|~36~1~1~4
- 5 - C 15 OR2 1 3 1 6 |74244:30|~36~1~1
- 4 - C 02 OR2 1 3 0 1 |74257:5|:2
- 8 - C 11 OR2 1 3 0 1 |74257:5|:4
- 1 - C 05 OR2 1 3 0 1 |74257:5|:33
- 7 - C 04 OR2 1 3 0 1 |74257:5|:34
- 3 - C 22 OR2 1 3 0 1 |74257:6|:6
- 5 - C 07 OR2 1 3 0 1 |74257:6|:35
- 4 - B 12 DFFE 0 2 0 2 |74273:22|Q8 (|74273:22|:12)
- 6 - C 06 DFFE 0 2 0 2 |74273:22|Q7 (|74273:22|:13)
- 6 - C 11 DFFE 0 2 0 4 |74273:22|Q6 (|74273:22|:14)
- 4 - C 08 DFFE 0 2 0 7 |74273:22|Q5 (|74273:22|:15)
- 1 - C 24 DFFE 0 2 0 9 |74273:22|Q4 (|74273:22|:16)
- 4 - C 09 DFFE 0 2 0 10 |74273:22|Q3 (|74273:22|:17)
- 7 - B 01 DFFE 0 2 0 13 |74273:22|Q2 (|74273:22|:18)
- 5 - C 09 DFFE 0 2 0 13 |74273:22|Q1 (|74273:22|:19)
- 5 - B 12 DFFE 0 2 0 1 |74273:23|Q8 (|74273:23|:12)
- 4 - C 06 DFFE 0 2 0 2 |74273:23|Q7 (|74273:23|:13)
- 2 - C 10 AND2 s 0 4 0 1 |74273:23|Q6~1 (|74273:23|~14~1)
- 7 - C 10 DFFE 0 2 0 5 |74273:23|Q6 (|74273:23|:14)
- 3 - C 01 AND2 s 0 4 0 2 |74273:23|Q5~1 (|74273:23|~15~1)
- 5 - C 01 DFFE 0 2 0 7 |74273:23|Q5 (|74273:23|:15)
- 1 - C 12 AND2 s 0 4 0 1 |74273:23|Q4~1 (|74273:23|~16~1)
- 8 - C 09 DFFE 0 2 0 9 |74273:23|Q4 (|74273:23|:16)
- 2 - C 09 DFFE 0 2 0 12 |74273:23|Q3 (|74273:23|:17)
- 4 - B 03 DFFE 0 2 0 13 |74273:23|Q2 (|74273:23|:18)
- 1 - C 09 DFFE 0 2 0 13 |74273:23|Q1 (|74273:23|:19)
- 5 - C 23 DFFE 0 2 0 1 |74374:24|:13
- 3 - C 17 DFFE 0 2 0 1 |74374:24|:14
- 1 - C 17 DFFE 0 2 0 1 |74374:24|:15
- 1 - C 13 DFFE 0 2 0 1 |74374:24|:16
- 1 - C 23 DFFE 0 2 0 1 |74374:24|:17
- 1 - C 19 DFFE 0 2 0 1 |74374:24|:18
- 6 - C 17 DFFE 0 2 0 1 |74374:24|:19
- 5 - C 17 DFFE 0 2 0 1 |74374:24|:20
- 3 - C 23 DFFE 0 2 0 1 |74374:25|:13
- 7 - C 14 DFFE 0 2 0 1 |74374:25|:14
- 6 - C 21 DFFE 0 2 0 1 |74374:25|:15
- 8 - C 16 DFFE 0 2 0 1 |74374:25|:16
- 3 - C 20 DFFE 0 2 0 1 |74374:25|:17
- 5 - C 20 DFFE 0 2 0 1 |74374:25|:18
- 5 - C 21 DFFE 0 2 0 1 |74374:25|:19
- 4 - B 14 DFFE 0 2 0 1 |74374:25|:20
- 6 - C 18 DFFE 0 2 0 1 |74374:26|:13
- 6 - C 14 DFFE 0 2 0 1 |74374:26|:14
- 1 - C 22 DFFE 0 2 0 1 |74374:26|:15
- 7 - C 16 DFFE 0 2 0 1 |74374:26|:16
- 1 - C 20 DFFE 0 2 0 1 |74374:26|:17
- 4 - C 20 DFFE 0 2 0 1 |74374:26|:18
- 8 - C 21 DFFE 0 2 0 1 |74374:26|:19
- 3 - B 14 DFFE 0 2 0 1 |74374:26|:20
- 5 - C 18 DFFE 0 2 0 1 |74374:27|:13
- 8 - C 15 DFFE 0 2 0 1 |74374:27|:14
- 4 - C 22 DFFE 0 2 0 1 |74374:27|:15
- 3 - C 15 DFFE 0 2 0 1 |74374:27|:16
- 2 - C 15 DFFE 0 2 0 1 |74374:27|:17
- 8 - C 04 DFFE 0 2 0 1 |74374:27|:18
- 4 - C 15 DFFE 0 2 0 1 |74374:27|:19
- 2 - B 18 DFFE 0 2 0 1 |74374:27|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\yunsuan33.rpt
yunsuan33
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 3/ 48( 6%) 7/16( 43%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 5/ 48( 10%) 9/ 48( 18%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
C: 38/ 96( 39%) 42/ 48( 87%) 26/ 48( 54%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 8/24( 33%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\yunsuan33.rpt
yunsuan33
** CLOCK SIGNALS **
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -