📄 yunsuan.rpt
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Device-Specific Information: d:\computer\alu\yunsuan.rpt
yunsuan
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - -- INPUT 0 0 0 9 ALU-BUS
53 - - - 20 BIDIR 0 1 0 6 BUS0
83 - - - 13 BIDIR 0 1 0 6 BUS1
21 - - B -- BIDIR 0 1 0 6 BUS2
24 - - B -- BIDIR 0 1 0 6 BUS3
25 - - B -- BIDIR 0 1 0 6 BUS4
23 - - B -- BIDIR 0 1 0 6 BUS5
66 - - B -- BIDIR 0 1 0 6 BUS6
59 - - C -- BIDIR 0 1 0 6 BUS7
1 - - - -- INPUT G 0 0 0 0 CLK
65 - - B -- INPUT 0 0 0 8 CLRN
81 - - - 22 INPUT 0 0 0 2 CN
17 - - A -- INPUT 0 0 0 1 DR0
71 - - A -- INPUT 0 0 0 1 DR1
19 - - A -- INPUT 0 0 0 1 DR2
73 - - A -- INPUT 0 0 0 1 DR3
64 - - B -- INPUT 0 0 0 6 EN
78 - - - 24 INPUT 0 0 0 1 LDDR1
54 - - - 21 INPUT 0 0 0 1 LDDR2
16 - - A -- INPUT 0 0 0 4 LDRI
67 - - B -- INPUT 0 0 0 8 M
2 - - - -- INPUT 0 0 0 11 MUL
69 - - A -- INPUT 0 0 0 5 RI-BUS
18 - - A -- INPUT 0 0 0 2 SELRI
44 - - - -- INPUT 0 0 0 9 SW-BUS
22 - - B -- INPUT 0 0 0 8 S0
47 - - - 14 INPUT 0 0 0 8 S1
84 - - - -- INPUT 0 0 0 8 S2
43 - - - -- INPUT 0 0 0 8 S3
48 - - - 15 INPUT 0 0 0 6 T2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\computer\alu\yunsuan.rpt
yunsuan
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
53 - - - 20 TRI 0 1 0 6 BUS0
83 - - - 13 TRI 0 1 0 6 BUS1
21 - - B -- TRI 0 1 0 6 BUS2
24 - - B -- TRI 0 1 0 6 BUS3
25 - - B -- TRI 0 1 0 6 BUS4
23 - - B -- TRI 0 1 0 6 BUS5
66 - - B -- TRI 0 1 0 6 BUS6
59 - - C -- TRI 0 1 0 6 BUS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\yunsuan.rpt
yunsuan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 01 DFFE + 1 2 0 3 |cdu:28|cdu16:1|74163:1|f74163:sub|QA (|cdu:28|cdu16:1|74163:1|f74163:sub|:34)
- 5 - B 01 DFFE + 1 2 0 2 |cdu:28|cdu16:1|74163:1|f74163:sub|QB (|cdu:28|cdu16:1|74163:1|f74163:sub|:111)
- 1 - B 01 AND2 0 4 0 2 |cdu:28|cdu16:1|74163:1|f74163:sub|:119
- 6 - B 15 DFFE + 1 1 0 2 |cdu:28|cdu16:1|74163:1|f74163:sub|QC (|cdu:28|cdu16:1|74163:1|f74163:sub|:122)
- 4 - B 15 DFFE + 1 2 0 1 |cdu:28|cdu16:1|74163:1|f74163:sub|QD (|cdu:28|cdu16:1|74163:1|f74163:sub|:134)
- 2 - B 19 DFFE + 2 0 0 4 |cdu:28|cdu16:2|74163:1|f74163:sub|QA (|cdu:28|cdu16:2|74163:1|f74163:sub|:34)
- 8 - B 01 AND2 1 2 0 1 |cdu:28|cdu16:2|74163:1|f74163:sub|:106
- 4 - B 19 DFFE + 2 1 0 3 |cdu:28|cdu16:2|74163:1|f74163:sub|QB (|cdu:28|cdu16:2|74163:1|f74163:sub|:111)
- 6 - B 01 AND2 1 3 0 4 |cdu:28|cdu16:2|74163:1|f74163:sub|:117
- 2 - B 01 DFFE + 2 1 0 2 |cdu:28|cdu16:2|74163:1|f74163:sub|QC (|cdu:28|cdu16:2|74163:1|f74163:sub|:122)
- 7 - B 01 AND2 0 2 0 1 |cdu:28|cdu16:2|74163:1|f74163:sub|:128
- 3 - B 01 DFFE + 2 1 0 4 |cdu:28|cdu16:2|74163:1|f74163:sub|QD (|cdu:28|cdu16:2|74163:1|f74163:sub|:134)
- 4 - B 14 OR2 0 4 0 1 |MULTI:60|one_bit_adder:U_0_0|:7
- 3 - B 02 AND2 0 4 0 3 |MULTI:60|one_bit_adder:U_0_0|:12
- 5 - B 02 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_1|:8
- 2 - B 02 AND2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_1|:12
- 6 - B 02 OR2 0 3 0 1 |MULTI:60|one_bit_adder:U_0_1|:15
- 4 - B 02 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_2|:8
- 7 - B 02 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_2|:13
- 1 - B 02 OR2 0 3 0 4 |MULTI:60|one_bit_adder:U_0_2|:15
- 2 - B 07 OR2 0 4 0 4 |MULTI:60|one_bit_adder:U_0_3|:13
- 8 - B 07 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_4|:8
- 3 - B 07 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_0_4|:13
- 6 - B 07 OR2 0 4 0 1 |MULTI:60|one_bit_adder:U_0_4|:14
- 2 - B 08 AND2 0 3 0 2 |MULTI:60|one_bit_adder:U_1_0|:12
- 4 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_1_1|:8
- 5 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_1_1|:15
- 7 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_1_2|:8
- 3 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_1_2|:15
- 2 - B 12 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_1_3|:8
- 3 - B 12 OR2 0 4 0 1 |MULTI:60|one_bit_adder:U_1_3|:15
- 8 - B 11 AND2 0 3 0 2 |MULTI:60|one_bit_adder:U_2_0|:12
- 1 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_2_1|:8
- 2 - B 11 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_2_1|:15
- 4 - B 12 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_2_2|:8
- 1 - B 12 OR2 0 4 0 1 |MULTI:60|one_bit_adder:U_2_2|:15
- 1 - B 06 AND2 0 3 0 2 |MULTI:60|one_bit_adder:U_3_0|:12
- 6 - B 12 OR2 0 4 0 2 |MULTI:60|one_bit_adder:U_3_1|:8
- 5 - B 12 OR2 0 4 0 1 |MULTI:60|one_bit_adder:U_3_1|:15
- 2 - B 24 OR2 s 0 4 0 1 |MULTI:60|one_bit_adder:U_4_1|~8~1
- 5 - B 07 OR2 s 0 4 0 1 |MULTI:60|one_bit_adder:U_4_1|~8~2
- 1 - B 07 OR2 s 0 4 0 1 |MULTI:60|one_bit_adder:U_4_1|~8~3
- 8 - B 12 OR2 s 0 4 0 1 |MULTI:60|one_bit_adder:U_4_1|~8~4
- 7 - B 12 OR2 s 0 4 0 1 |MULTI:60|one_bit_adder:U_4_1|~8~5
- 2 - B 05 AND2 0 2 0 1 |MULTI:60|:1401
- 6 - B 11 AND2 0 2 0 2 |MULTI:60|:1716
- 2 - B 04 AND2 0 2 0 1 |MULTI:60|:1830
- 1 - A 13 OR2 3 0 0 7 |risel:32|2sel1:17|Y1 (|risel:32|2sel1:17|:101)
- 2 - A 13 OR2 3 0 0 7 |risel:32|2sel1:17|Y2 (|risel:32|2sel1:17|:102)
- 3 - A 18 AND2 2 2 0 8 |risel:32|R1LD (|risel:32|:8)
- 1 - A 18 AND2 2 2 0 8 |risel:32|R2LD (|risel:32|:9)
- 7 - A 18 AND2 2 2 0 8 |risel:32|R3LD (|risel:32|:10)
- 6 - A 18 AND2 3 0 0 8 |risel:32|R4LD (|risel:32|:11)
- 5 - A 18 AND2 1 2 0 9 |risel:32|:19
- 4 - A 18 AND2 1 2 0 9 |risel:32|:20
- 2 - A 18 AND2 1 2 0 9 |risel:32|:21
- 8 - A 18 AND2 1 2 0 9 |risel:32|:22
- 2 - B 18 AND2 2 0 0 8 :24
- 2 - B 22 AND2 2 0 0 8 :26
- 8 - B 24 OR2 ! 2 2 0 2 |74181:11|:43
- 1 - B 24 OR2 ! 2 2 0 3 |74181:11|:44
- 6 - B 24 OR2 ! 2 2 0 2 |74181:11|:45
- 3 - B 23 OR2 ! 2 2 0 2 |74181:11|:46
- 5 - B 13 OR2 ! 2 2 0 3 |74181:11|:47
- 6 - B 17 OR2 ! 2 2 0 2 |74181:11|:48
- 4 - B 24 OR2 ! 2 2 0 3 |74181:11|:51
- 5 - B 20 OR2 ! 2 2 0 3 |74181:11|:52
- 8 - B 17 OR2 1 3 0 1 |74181:11|:75
- 3 - B 20 OR2 1 3 0 1 |74181:11|:77
- 1 - B 17 OR2 s 1 2 0 3 |74181:11|CN4~1 (|74181:11|~78~1)
- 5 - B 17 OR2 s 0 2 0 1 |74181:11|CN4~2 (|74181:11|~78~2)
- 3 - B 17 OR2 s 0 4 0 3 |74181:11|CN4~3 (|74181:11|~78~3)
- 7 - B 17 OR2 2 2 0 1 |74181:11|:80
- 4 - B 17 OR2 1 3 0 1 |74181:11|:81
- 5 - B 24 OR2 ! 2 2 0 3 |74181:13|:43
- 3 - B 13 OR2 ! 2 2 0 2 |74181:13|:44
- 2 - B 13 OR2 2 2 0 2 |74181:13|:45
- 6 - B 20 OR2 ! 2 2 0 2 |74181:13|:46
- 4 - B 13 OR2 ! 2 2 0 2 |74181:13|:47
- 1 - B 13 OR2 2 2 0 2 |74181:13|:48
- 1 - B 23 OR2 s 2 1 0 1 |74181:13|~51~1
- 2 - B 23 OR2 s 2 1 0 1 |74181:13|~52~1
- 8 - B 20 OR2 1 3 0 1 |74181:13|:64
- 7 - B 20 OR2 s 0 4 0 2 |74181:13|~69~1
- 1 - B 21 OR2 1 3 0 1 |74181:13|:74
- 1 - B 20 OR2 s 0 4 0 2 |74181:13|~75~1
- 8 - B 23 OR2 0 4 0 1 |74181:13|:77
- 2 - B 20 OR2 1 2 0 1 |74181:13|:79
- 4 - B 21 OR2 1 3 0 1 |74181:13|:82
- 5 - C 23 OR2 s 0 4 0 1 |74244:1|~1~1~3~2
- 4 - C 23 OR2 s 0 3 0 1 |74244:1|~1~1~3~3
- 3 - B 19 OR2 s 2 2 0 1 |74244:1|~1~1~3~4
- 5 - B 19 OR2 0 4 1 0 |74244:1|~1~1~3
- 1 - B 14 OR2 s 0 4 0 1 |74244:1|~6~1~3~2
- 2 - B 14 OR2 s 1 3 0 1 |74244:1|~6~1~3~3
- 3 - B 14 OR2 s 0 3 0 1 |74244:1|~6~1~3~4
- 5 - B 14 AND2 0 3 1 0 |74244:1|~6~1~3
- 1 - B 03 OR2 s 0 4 0 1 |74244:1|~10~1~3~2
- 3 - B 08 OR2 s 1 3 0 1 |74244:1|~10~1~3~3
- 4 - B 08 OR2 s 0 4 0 1 |74244:1|~10~1~3~4
- 1 - B 08 OR2 1 3 1 0 |74244:1|~10~1~3
- 1 - B 04 OR2 s 0 4 0 1 |74244:1|~11~1~3~2
- 1 - B 09 OR2 s 1 3 0 1 |74244:1|~11~1~3~3
- 2 - B 09 OR2 s 0 3 0 1 |74244:1|~11~1~3~4
- 6 - B 04 OR2 1 3 1 0 |74244:1|~11~1~3
- 2 - C 23 OR2 s 0 4 0 1 |74244:1|~26~1~3~2
- 1 - B 15 OR2 s 1 3 0 1 |74244:1|~26~1~3~3
- 1 - C 15 OR2 s 0 4 0 1 |74244:1|~26~1~3~4
- 5 - C 15 OR2 2 2 1 0 |74244:1|~26~1~3
- 3 - C 23 OR2 s 0 3 0 1 |74244:1|~27~1~2~2
- 1 - C 23 OR2 2 2 0 0 |74244:1|~27~1~2
- 2 - B 21 OR2 s 0 4 0 1 |74244:1|~27~1~3~2
- 2 - B 15 OR2 s 1 3 0 1 |74244:1|~27~1~3~3
- 4 - B 16 OR2 s 0 3 0 1 |74244:1|~27~1~3~4
- 3 - B 21 OR2 1 3 1 0 |74244:1|~27~1~3
- 2 - B 10 OR2 s 0 4 0 1 |74244:1|~31~1~3~2
- 3 - B 10 OR2 s 1 3 0 1 |74244:1|~31~1~3~3
- 5 - B 10 OR2 s 0 4 0 1 |74244:1|~31~1~3~4
- 4 - B 10 OR2 1 3 1 0 |74244:1|~31~1~3
- 2 - B 03 OR2 s 0 4 0 1 |74244:1|~36~1~3~2
- 3 - B 06 OR2 s 1 3 0 1 |74244:1|~36~1~3~3
- 4 - B 06 OR2 s 0 4 0 1 |74244:1|~36~1~3~4
- 8 - B 06 OR2 1 3 1 0 |74244:1|~36~1~3
- 1 - B 19 OR2 s 1 3 0 1 |74244:15|~1~1~1
- 6 - B 14 OR2 2 2 0 1 |74244:15|~6~1
- 3 - B 04 OR2 s 1 3 0 1 |74244:15|~11~1~1
- 6 - B 21 OR2 s 1 3 0 1 |74244:15|~27~1~1
- 5 - B 08 OR2 1 3 0 1 |74257:61|:6
- 2 - B 17 OR2 1 3 0 1 |74257:61|:35
- 2 - B 06 OR2 1 3 0 1 |74257:71|:2
- 1 - B 10 OR2 1 3 0 1 |74257:71|:4
- 4 - B 20 OR2 1 3 0 1 |74257:71|:33
- 6 - B 10 OR2 1 3 0 1 |74257:71|:34
- 7 - B 23 DFFE 0 2 0 1 |74273:7|Q8 (|74273:7|:12)
- 6 - B 13 DFFE 0 2 0 2 |74273:7|Q7 (|74273:7|:13)
- 7 - B 07 AND2 s 0 4 0 1 |74273:7|Q6~1 (|74273:7|~14~1)
- 6 - B 18 DFFE 0 2 0 5 |74273:7|Q6 (|74273:7|:14)
- 4 - B 07 AND2 s 0 4 0 2 |74273:7|Q5~1 (|74273:7|~15~1)
- 8 - B 18 DFFE 0 2 0 7 |74273:7|Q5 (|74273:7|:15)
- 8 - B 02 AND2 s 0 4 0 1 |74273:7|Q4~1 (|74273:7|~16~1)
- 5 - B 18 DFFE 0 2 0 9 |74273:7|Q4 (|74273:7|:16)
- 7 - B 18 DFFE 0 2 0 12 |74273:7|Q3 (|74273:7|:17)
- 7 - B 13 DFFE 0 2 0 13 |74273:7|Q2 (|74273:7|:18)
- 5 - B 23 DFFE 0 2 0 13 |74273:7|Q1 (|74273:7|:19)
- 6 - B 23 DFFE 0 2 0 2 |74273:10|Q8 (|74273:10|:12)
- 8 - B 13 DFFE 0 2 0 2 |74273:10|Q7 (|74273:10|:13)
- 5 - B 22 DFFE 0 2 0 4 |74273:10|Q6 (|74273:10|:14)
- 8 - B 22 DFFE 0 2 0 7 |74273:10|Q5 (|74273:10|:15)
- 4 - B 22 DFFE 0 2 0 9 |74273:10|Q4 (|74273:10|:16)
- 6 - B 22 DFFE 0 2 0 10 |74273:10|Q3 (|74273:10|:17)
- 1 - B 22 DFFE 0 2 0 13 |74273:10|Q2 (|74273:10|:18)
- 4 - B 23 DFFE 0 2 0 13 |74273:10|Q1 (|74273:10|:19)
- 8 - C 23 DFFE 0 2 0 1 |74374:2|:13
- 5 - B 21 DFFE 0 2 0 1 |74374:2|:14
- 7 - B 08 DFFE 0 2 0 1 |74374:2|:15
- 4 - B 09 DFFE 0 2 0 1 |74374:2|:16
- 6 - B 06 DFFE 0 2 0 1 |74374:2|:17
- 8 - B 10 DFFE 0 2 0 1 |74374:2|:18
- 7 - B 21 DFFE 0 2 0 1 |74374:2|:19
- 2 - C 15 DFFE 0 2 0 1 |74374:2|:20
- 1 - C 17 DFFE 0 2 0 1 |74374:4|:13
- 8 - B 21 DFFE 0 2 0 1 |74374:4|:14
- 4 - B 03 DFFE 0 2 0 1 |74374:4|:15
- 7 - B 03 DFFE 0 2 0 1 |74374:4|:16
- 4 - B 04 DFFE 0 2 0 1 |74374:4|:17
- 5 - B 03 DFFE 0 2 0 1 |74374:4|:18
- 7 - B 14 DFFE 0 2 0 1 |74374:4|:19
- 6 - B 19 DFFE 0 2 0 1 |74374:4|:20
- 1 - C 22 DFFE 0 2 0 1 |74374:5|:13
- 1 - C 19 DFFE 0 2 0 1 |74374:5|:14
- 6 - B 08 DFFE 0 2 0 1 |74374:5|:15
- 3 - B 09 DFFE 0 2 0 1 |74374:5|:16
- 5 - B 06 DFFE 0 2 0 1 |74374:5|:17
- 7 - B 10 DFFE 0 2 0 1 |74374:5|:18
- 5 - B 15 DFFE 0 2 0 1 |74374:5|:19
- 3 - B 15 DFFE 0 2 0 1 |74374:5|:20
- 6 - C 23 DFFE 0 2 0 1 |74374:6|:13
- 1 - B 16 DFFE 0 2 0 1 |74374:6|:14
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