shixu.vhd

vhd语言

--shixu.vhd
LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shixu is
  port (  clk,tj,dp,qd:in std_logic;
          t1,t2,t3,t4:out std_logic
      );
end shixu;


architecture  a of shixu is
   signal qk     :std_logic_vector(3 downto 0);
   signal lian,dan,he,go,rst,hi : std_logic;
   signal qq     :std_logic_vector(2 downto 0);
begin
  ld :process(dp,qd,rst)                                   
  begin
      hi<=not qd;
   if rst='1'then  go<='0';
  elsif qd'event and qd='0'then go<='1';
   if dp='1' then
      lian<='0';   dan<='1';
  else  lian<='1';   dan<='0';
  end if;
  end if;
  end process ld;


  qid :process(clk,he,qd)
begin
  if he='1'then  qq<="111";
  elsif clk'event and clk='1'then
     if go='1'and qd='0'then qq<=qq+1;
     end if;
  end if;
 end process qid;
 he<='1' when ((qq=4) or tj='1')else'0';
rst<='1'when(qq=4)and((dan='1'or qd='1')or dp='1')else'0';
qk<="0001"when qq=0 else
    "0010"when qq=1 else
    "0100"when qq=2 else
    "1000"when qq=3 else
    "0000";
t1<=qk(0) and (not tj);
t2<=qk(1) and (not tj);
t3<=qk(2) and (not tj);
t4<=qk(3) and (not tj);
end a;