📄 kongceshi2.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 66/ 96( 68%) 27/ 48( 56%) 31/ 48( 64%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 2/ 96( 2%) 10/ 48( 20%) 1/ 48( 2%) 1/16( 6%) 7/16( 43%) 0/16( 0%)
C: 17/ 96( 17%) 12/ 48( 25%) 8/ 48( 16%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 37 |shixudianlu:89|T2
LCELL 8 :49
DFF 4 |shixudianlu:89|74175:13|4Q
INPUT 3 CLK
LCELL 3 |shixudianlu:89|:25
Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 44 CLR
LCELL 3 |shixudianlu:89|:26
Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
DP : INPUT;
QD : INPUT;
R0 : INPUT;
R1 : INPUT;
R2 : INPUT;
R3 : INPUT;
R4 : INPUT;
R5 : INPUT;
R6 : INPUT;
R7 : INPUT;
TJ : INPUT;
-- Node name is 'ALU_BUS'
-- Equation name is 'ALU_BUS', type is output
ALU_BUS = _LC7_A1;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = _LC8_A23;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC5_C13;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = _LC1_A4;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = _LC6_C8;
-- Node name is 'A4'
-- Equation name is 'A4', type is output
A4 = _LC4_A21;
-- Node name is 'A5'
-- Equation name is 'A5', type is output
A5 = _LC2_A12;
-- Node name is 'CN'
-- Equation name is 'CN', type is output
CN = _LC1_A16;
-- Node name is 'DAT0'
-- Equation name is 'DAT0', type is output
DAT0 = _LC2_A4;
-- Node name is 'DAT1'
-- Equation name is 'DAT1', type is output
DAT1 = _LC8_C8;
-- Node name is 'DAT2'
-- Equation name is 'DAT2', type is output
DAT2 = _LC1_C15;
-- Node name is 'DAT3'
-- Equation name is 'DAT3', type is output
DAT3 = _LC1_C10;
-- Node name is 'LDAR'
-- Equation name is 'LDAR', type is output
LDAR = _LC5_A21;
-- Node name is 'LDDR1'
-- Equation name is 'LDDR1', type is output
LDDR1 = _LC5_A20;
-- Node name is 'LDDR2'
-- Equation name is 'LDDR2', type is output
LDDR2 = _LC2_A16;
-- Node name is 'LDIR'
-- Equation name is 'LDIR', type is output
LDIR = _LC8_B11;
-- Node name is 'LDRI'
-- Equation name is 'LDRI', type is output
LDRI = _LC1_A20;
-- Node name is 'M'
-- Equation name is 'M', type is output
M = GND;
-- Node name is 'MUL'
-- Equation name is 'MUL', type is output
MUL = _LC8_A17;
-- Node name is 'PC_BUS'
-- Equation name is 'PC_BUS', type is output
PC_BUS = _LC7_A5;
-- Node name is 'P1'
-- Equation name is 'P1', type is output
P1 = _LC7_C21;
-- Node name is 'P2'
-- Equation name is 'P2', type is output
P2 = _LC6_A23;
-- Node name is 'P3'
-- Equation name is 'P3', type is output
P3 = _LC3_C8;
-- Node name is 'RD'
-- Equation name is 'RD', type is output
RD = _LC8_A21;
-- Node name is 'RI_BUS'
-- Equation name is 'RI_BUS', type is output
RI_BUS = _LC8_A13;
-- Node name is 'SELRI'
-- Equation name is 'SELRI', type is output
SELRI = _LC7_A16;
-- Node name is 'SW_BUS'
-- Equation name is 'SW_BUS', type is output
SW_BUS = _LC4_A6;
-- Node name is 'S0'
-- Equation name is 'S0', type is output
S0 = _LC6_A1;
-- Node name is 'S1'
-- Equation name is 'S1', type is output
S1 = _LC8_A16;
-- Node name is 'S2'
-- Equation name is 'S2', type is output
S2 = _LC6_A12;
-- Node name is 'S3'
-- Equation name is 'S3', type is output
S3 = _LC3_A1;
-- Node name is 'T1'
-- Equation name is 'T1', type is output
T1 = _LC2_B11;
-- Node name is 'T2'
-- Equation name is 'T2', type is output
T2 = _LC7_B11;
-- Node name is 'T3'
-- Equation name is 'T3', type is output
T3 = _LC5_B11;
-- Node name is 'T4'
-- Equation name is 'T4', type is output
T4 = _LC4_B4;
-- Node name is 'WE'
-- Equation name is 'WE', type is output
WE = _LC5_A2;
-- Node name is '161CLRN'
-- Equation name is '161CLRN', type is output
161CLRN = _LC5_A24;
-- Node name is '161LOAD'
-- Equation name is '161LOAD', type is output
161LOAD = _LC5_A6;
-- Node name is '161PC'
-- Equation name is '161PC', type is output
161PC = _LC4_A5;
-- Node name is '|p1:8|:4'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = LCELL( _EQ001);
_EQ001 = !_LC7_C21
# !_LC4_B4
# !_LC1_C21;
-- Node name is '|p1:8|:5'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = LCELL( _EQ002);
_EQ002 = !_LC2_C21
# !_LC7_C21
# !_LC4_B4;
-- Node name is '|p1:8|:6'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ003);
_EQ003 = !_LC7_C21
# !_LC4_B4
# !_LC1_C13;
-- Node name is '|p1:8|:12'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ004);
_EQ004 = !_LC7_C21
# !_LC4_B4
# !_LC6_C21;
-- Node name is '|p1:8|7474:1|:9' = '|p1:8|7474:1|1Q'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = DFFE( _EQ005, _LC7_B11, GLOBAL( CLR), VCC, VCC);
_EQ005 = !_LC5_A14 & _LC7_A12 & !_LC8_A14
# !_LC5_A14 & _LC7_A7 & !_LC8_A14;
-- Node name is '|p1:8|7474:1|:10' = '|p1:8|7474:1|2Q'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = DFFE( _EQ006, _LC7_B11, GLOBAL( CLR), VCC, VCC);
_EQ006 = !_LC5_A14 & _LC6_A21 & !_LC7_A7 & !_LC8_A14;
-- Node name is '|p1:8|7474:2|:9' = '|p1:8|7474:2|1Q'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _EQ007, _LC7_B11, GLOBAL( CLR), _LC3_C21, VCC);
_EQ007 = _LC5_A12 & _LC7_A8 & !_LC8_A11;
-- Node name is '|p1:8|7474:2|:10' = '|p1:8|7474:2|2Q'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = DFFE( _EQ008, _LC7_B11, GLOBAL( CLR), _LC5_C21, VCC);
_EQ008 = _LC5_A12 & _LC7_A4;
-- Node name is '|p1:8|7474:3|:9' = '|p1:8|7474:3|1Q'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ009, _LC7_B11, GLOBAL( CLR), _LC2_C13, VCC);
_EQ009 = _LC3_C13 & !_LC8_A14
# _LC5_A14 & !_LC8_A14;
-- Node name is '|p1:8|7474:3|:10' = '|p1:8|7474:3|2Q'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ010, _LC7_B11, GLOBAL( CLR), _LC8_C21, VCC);
_EQ010 = _LC2_A23 & _LC5_A18
# _LC8_A14;
-- Node name is '|p2:7|:10'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = LCELL( _EQ011);
_EQ011 = !_LC1_C10
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