📄 kongceshi2.rpt
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Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - - 02 OUTPUT 0 1 0 0 ALU_BUS
69 - - A -- OUTPUT 0 1 0 0 A0
47 - - - 14 OUTPUT 0 1 0 0 A1
16 - - A -- OUTPUT 0 1 0 0 A2
36 - - - 07 OUTPUT 0 1 0 0 A3
71 - - A -- OUTPUT 0 1 0 0 A4
72 - - A -- OUTPUT 0 1 0 0 A5
73 - - A -- OUTPUT 0 1 0 0 CN
28 - - C -- OUTPUT 0 1 0 0 DAT0
29 - - C -- OUTPUT 0 1 0 0 DAT1
62 - - C -- OUTPUT 0 1 0 0 DAT2
27 - - C -- OUTPUT 0 1 0 0 DAT3
54 - - - 21 OUTPUT 0 1 0 0 LDAR
53 - - - 20 OUTPUT 0 1 0 0 LDDR1
66 - - B -- OUTPUT 0 1 0 0 LDDR2
25 - - B -- OUTPUT 0 1 0 0 LDIR
52 - - - 19 OUTPUT 0 1 0 0 LDRI
67 - - B -- OUTPUT 0 0 0 0 M
51 - - - 18 OUTPUT 0 1 0 0 MUL
19 - - A -- OUTPUT 0 1 0 0 PC_BUS
58 - - C -- OUTPUT 0 1 0 0 P1
79 - - - 24 OUTPUT 0 1 0 0 P2
23 - - B -- OUTPUT 0 1 0 0 P3
81 - - - 22 OUTPUT 0 1 0 0 RD
83 - - - 13 OUTPUT 0 1 0 0 RI_BUS
48 - - - 15 OUTPUT 0 1 0 0 SELRI
35 - - - 06 OUTPUT 0 1 0 0 SW_BUS
24 - - B -- OUTPUT 0 1 0 0 S0
70 - - A -- OUTPUT 0 1 0 0 S1
39 - - - 11 OUTPUT 0 1 0 0 S2
17 - - A -- OUTPUT 0 1 0 0 S3
22 - - B -- OUTPUT 0 1 0 0 T1
3 - - - 12 OUTPUT 0 1 0 0 T2
65 - - B -- OUTPUT 0 1 0 0 T3
7 - - - 03 OUTPUT 0 1 0 0 T4
10 - - - 01 OUTPUT 0 1 0 0 WE
78 - - - 24 OUTPUT 0 1 0 0 161CLRN
18 - - A -- OUTPUT 0 1 0 0 161LOAD
5 - - - 05 OUTPUT 0 1 0 0 161PC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 21 OR2 0 3 0 1 |p1:8|:4
- 5 - C 21 OR2 0 3 0 1 |p1:8|:5
- 2 - C 13 OR2 0 3 0 1 |p1:8|:6
- 8 - C 21 OR2 0 3 0 1 |p1:8|:12
- 2 - A 12 DFFE 0 5 1 27 |p1:8|7474:1|1Q (|p1:8|7474:1|:9)
- 4 - A 21 DFFE 0 5 1 20 |p1:8|7474:1|2Q (|p1:8|7474:1|:10)
- 4 - C 02 DFFE 0 5 0 1 |p1:8|7474:2|1Q (|p1:8|7474:2|:9)
- 4 - C 21 DFFE 0 4 0 1 |p1:8|7474:2|2Q (|p1:8|7474:2|:10)
- 4 - C 13 DFFE 0 5 0 1 |p1:8|7474:3|1Q (|p1:8|7474:3|:9)
- 3 - A 23 DFFE 0 5 0 1 |p1:8|7474:3|2Q (|p1:8|7474:3|:10)
- 2 - C 10 OR2 0 3 0 1 |p2:7|:10
- 3 - C 15 OR2 0 3 0 1 |p2:7|:11
- 8 - C 10 DFFE 0 5 0 1 |p2:7|7474:8|1Q (|p2:7|7474:8|:9)
- 4 - C 15 DFFE 0 4 0 1 |p2:7|7474:8|2Q (|p2:7|7474:8|:10)
- 2 - C 08 OR2 0 3 0 1 |p3:6|:10
- 6 - A 04 OR2 0 3 0 1 |p3:6|:11
- 4 - C 08 DFFE 0 5 0 1 |p3:6|7474:8|1Q (|p3:6|7474:8|:9)
- 8 - A 04 DFFE 0 4 0 1 |p3:6|7474:8|2Q (|p3:6|7474:8|:10)
- 6 - C 13 DFFE 0 4 0 1 |p3:6|7474:9|1Q (|p3:6|7474:9|:9)
- 4 - A 23 DFFE 0 4 0 1 |p3:6|7474:9|2Q (|p3:6|7474:9|:10)
- 8 - A 14 OR2 ! 0 3 0 13 |ROM:2|:146
- 5 - A 14 OR2 ! 0 4 0 11 |ROM:2|:153
- 7 - A 07 OR2 ! 0 4 0 12 |ROM:2|:160
- 4 - A 14 OR2 s 0 3 0 9 |ROM:2|~167~1
- 7 - A 14 OR2 ! 0 3 0 1 |ROM:2|:167
- 1 - A 14 OR2 ! 0 4 0 2 |ROM:2|:174
- 1 - A 11 OR2 ! 0 4 0 2 |ROM:2|:181
- 3 - A 11 OR2 ! 0 4 0 2 |ROM:2|:188
- 2 - A 08 AND2 0 4 0 4 |ROM:2|:195
- 3 - A 14 OR2 s 0 2 0 6 |ROM:2|~202~1
- 3 - A 08 AND2 0 4 0 4 |ROM:2|:202
- 5 - A 08 AND2 0 4 0 4 |ROM:2|:209
- 6 - A 09 OR2 ! 0 4 0 7 |ROM:2|:216
- 3 - A 10 OR2 ! 0 4 0 7 |ROM:2|:223
- 6 - A 10 OR2 ! 0 4 0 4 |ROM:2|:230
- 3 - A 02 OR2 ! 0 4 0 4 |ROM:2|:237
- 8 - A 07 OR2 ! 0 3 0 7 |ROM:2|:244
- 3 - A 12 OR2 ! 0 3 0 4 |ROM:2|:251
- 2 - A 09 OR2 s ! 0 3 0 4 |ROM:2|~258~1
- 1 - A 09 OR2 ! 0 4 0 5 |ROM:2|:258
- 2 - A 07 OR2 s 0 4 0 5 |ROM:2|~265~1
- 2 - A 24 OR2 ! 0 2 0 11 |ROM:2|:265
- 6 - A 07 OR2 s ! 0 2 0 5 |ROM:2|~272~1
- 4 - A 07 OR2 ! 0 4 0 9 |ROM:2|:272
- 7 - A 02 OR2 s 0 2 0 12 |ROM:2|~279~1
- 3 - A 07 OR2 ! 0 4 0 12 |ROM:2|:279
- 2 - A 10 AND2 0 4 0 8 |ROM:2|:286
- 2 - A 14 OR2 s 0 2 0 5 |ROM:2|~293~1
- 2 - A 02 OR2 ! 0 4 0 12 |ROM:2|:293
- 5 - A 07 OR2 s 0 2 0 5 |ROM:2|~300~1
- 1 - A 07 AND2 0 4 0 9 |ROM:2|:300
- 8 - A 03 OR2 ! 0 2 0 9 |ROM:2|:307
- 8 - A 09 AND2 0 4 0 8 |ROM:2|:314
- 3 - A 24 OR2 ! 0 2 0 6 |ROM:2|:321
- 4 - A 10 AND2 0 4 0 7 |ROM:2|:328
- 5 - A 10 OR2 ! 0 4 0 7 |ROM:2|:335
- 7 - A 09 AND2 0 3 0 7 |ROM:2|:342
- 8 - A 02 OR2 ! 0 4 0 8 |ROM:2|:349
- 7 - A 10 AND2 0 4 0 8 |ROM:2|:356
- 1 - A 03 OR2 s 0 3 0 3 |ROM:2|~363~1
- 1 - A 02 OR2 s 0 2 0 1 |ROM:2|~363~2
- 6 - A 03 OR2 ! 0 3 0 4 |ROM:2|:363
- 5 - A 09 AND2 0 3 0 5 |ROM:2|:370
- 5 - A 03 AND2 0 4 0 3 |ROM:2|:377
- 4 - A 09 AND2 s 0 2 0 7 |ROM:2|~384~1
- 4 - A 08 AND2 s 0 2 0 1 |ROM:2|~384~2
- 1 - A 08 AND2 0 4 0 7 |ROM:2|:384
- 6 - A 02 AND2 0 4 0 5 |ROM:2|:391
- 4 - A 02 OR2 s ! 0 2 0 8 |ROM:2|~398~1
- 8 - A 12 AND2 0 3 0 6 |ROM:2|:398
- 2 - A 01 AND2 s ! 0 2 0 3 |ROM:2|~624~1
- 7 - A 24 OR2 s 0 4 0 1 |ROM:2|~624~2
- 1 - A 06 OR2 0 4 0 1 |ROM:2|:641
- 2 - A 06 OR2 0 4 0 1 |ROM:2|:645
- 3 - A 06 OR2 0 4 0 1 |ROM:2|:659
- 4 - A 16 AND2 s ! 0 3 0 3 |ROM:2|~732~1
- 2 - A 19 OR2 0 4 0 3 |ROM:2|:768
- 1 - A 05 OR2 0 3 0 1 |ROM:2|:837
- 6 - A 06 OR2 0 4 0 1 |ROM:2|:858
- 8 - A 06 OR2 0 4 0 1 |ROM:2|:872
- 3 - A 05 OR2 0 4 0 1 |ROM:2|:876
- 4 - A 24 OR2 s 0 4 0 2 |ROM:2|~942~1
- 1 - A 24 OR2 s 0 3 0 3 |ROM:2|~942~2
- 5 - A 05 OR2 0 4 0 1 |ROM:2|:953
- 3 - A 19 OR2 0 2 0 1 |ROM:2|:978
- 6 - A 05 OR2 0 4 0 1 |ROM:2|:984
- 8 - A 05 OR2 0 3 0 1 |ROM:2|:990
- 7 - A 13 AND2 s 0 2 0 2 |ROM:2|~1028~1
- 4 - A 01 OR2 s ! 0 2 0 2 |ROM:2|~1028~2
- 2 - A 15 OR2 s ! 0 4 0 2 |ROM:2|~1028~3
- 6 - A 24 OR2 s ! 0 4 0 3 |ROM:2|~1028~4
- 7 - A 20 OR2 0 4 0 1 |ROM:2|:1034
- 3 - A 20 OR2 0 4 0 1 |ROM:2|:1059
- 4 - A 19 OR2 0 2 0 4 |ROM:2|:1197
- 8 - A 18 OR2 0 4 0 1 |ROM:2|:1211
- 3 - A 18 OR2 0 4 0 1 |ROM:2|:1250
- 8 - A 20 AND2 s ! 0 2 0 4 |ROM:2|~1254~1
- 7 - A 21 OR2 0 4 0 1 |ROM:2|:1286
- 7 - A 06 OR2 0 3 0 1 |ROM:2|:1304
- 4 - A 13 AND2 s ! 0 2 0 3 |ROM:2|~1398~1
- 2 - A 05 OR2 s 0 4 0 2 |ROM:2|~1398~2
- 5 - A 04 AND2 s ! 0 2 0 1 |ROM:2|~1497~1
- 6 - A 08 AND2 ! 0 4 0 8 |ROM:2|:1497
- 5 - A 12 AND2 s 0 4 0 11 |ROM:2|~1514~1
- 7 - A 22 OR2 s ! 0 3 0 1 |ROM:2|~1958~1
- 6 - A 16 AND2 s 0 2 0 5 |ROM:2|~1958~2
- 8 - A 01 OR2 0 2 0 1 |ROM:2|:2004
- 5 - A 16 OR2 s ! 0 2 0 3 |ROM:2|~2180~1
- 7 - A 18 OR2 s 0 3 0 2 |ROM:2|~2211~1
- 8 - A 24 OR2 0 4 0 1 |ROM:2|:2219
- 1 - A 01 OR2 0 4 0 1 |ROM:2|:2223
- 5 - A 01 OR2 0 4 0 1 |ROM:2|:2237
- 1 - A 13 OR2 0 2 0 1 |ROM:2|:2325
- 5 - A 15 OR2 0 4 0 1 |ROM:2|:2331
- 7 - A 15 OR2 0 4 0 1 |ROM:2|:2345
- 2 - A 20 OR2 0 4 0 1 |ROM:2|:2349
- 4 - A 20 OR2 0 4 0 1 |ROM:2|:2361
- 6 - A 20 AND2 s 0 3 0 2 |ROM:2|~2402~1
- 2 - A 18 OR2 s 0 2 0 1 |ROM:2|~2436~1
- 2 - A 13 OR2 0 4 0 1 |ROM:2|:2436
- 3 - A 13 OR2 0 4 0 1 |ROM:2|:2450
- 5 - A 13 OR2 0 4 0 1 |ROM:2|:2454
- 6 - A 13 OR2 0 4 0 1 |ROM:2|:2471
- 5 - A 22 AND2 s ! 0 4 0 3 |ROM:2|~2481~1
- 1 - A 15 OR2 0 4 0 1 |ROM:2|:2562
- 3 - A 16 OR2 0 4 0 2 |ROM:2|:2576
- 7 - A 12 OR2 0 4 0 1 |ROM:2|:3395
- 8 - A 15 OR2 0 3 0 2 |ROM:2|:3446
- 1 - A 21 OR2 0 4 0 1 |ROM:2|:3450
- 2 - A 21 OR2 0 4 0 1 |ROM:2|:3464
- 3 - A 21 OR2 0 4 0 1 |ROM:2|:3468
- 1 - A 12 OR2 s 0 2 0 1 |ROM:2|~3501~1
- 4 - A 12 OR2 s 0 4 0 2 |ROM:2|~3501~2
- 6 - A 21 OR2 0 4 0 1 |ROM:2|:3501
- 7 - A 19 OR2 0 2 0 3 |ROM:2|:3525
- 1 - A 19 OR2 0 4 0 2 |ROM:2|:3539
- 4 - A 18 OR2 0 4 0 1 |ROM:2|:3543
- 4 - A 15 OR2 0 4 0 1 |ROM:2|:3557
- 3 - A 15 OR2 0 4 0 1 |ROM:2|:3561
- 8 - A 08 OR2 s 0 3 0 1 |ROM:2|~3600~1
- 7 - A 08 OR2 0 4 0 3 |ROM:2|:3600
- 1 - A 23 AND2 s 0 3 0 1 |ROM:2|~3623~1
- 3 - A 04 OR2 0 3 0 1 |ROM:2|:3678
- 6 - A 15 AND2 s 0 3 0 1 |ROM:2|~3680~1
- 3 - A 17 AND2 s 0 2 0 3 |ROM:2|~3707~1
- 4 - A 04 OR2 0 4 0 1 |ROM:2|:3707
- 8 - A 11 AND2 s ! 0 2 0 5 |ROM:2|~3717~1
- 7 - A 04 OR2 0 4 0 3 |ROM:2|:3717
- 3 - A 22 OR2 0 4 0 1 |ROM:2|:3777
- 1 - A 18 AND2 s 0 3 0 3 |ROM:2|~3779~1
- 2 - A 22 AND2 s 0 3 0 1 |ROM:2|~3779~2
- 1 - A 22 AND2 s 0 3 0 1 |ROM:2|~3791~1
- 2 - A 17 AND2 s 0 2 0 4 |ROM:2|~3803~1
- 6 - A 22 OR2 0 4 0 1 |ROM:2|:3803
- 8 - A 22 OR2 0 4 0 1 |ROM:2|:3810
- 4 - A 22 OR2 0 4 0 1 |ROM:2|:3819
- 2 - A 11 OR2 0 4 0 1 |ROM:2|:3833
- 3 - C 13 OR2 0 4 0 2 |ROM:2|:3842
- 8 - A 19 OR2 0 4 0 2 |ROM:2|:3861
- 6 - A 18 OR2 0 4 0 1 |ROM:2|:3873
- 5 - A 18 OR2 0 4 0 2 |ROM:2|:3921
- 6 - A 14 OR2 s 0 4 0 8 |ROM:2|~3956~1
- 2 - A 23 AND2 s 0 3 0 2 |ROM:2|~3956~2
- 6 - B 04 OR2 s 2 1 0 1 |shixudianlu:89|~12~1
- 4 - B 04 OR2 ! 0 2 1 8 |shixudianlu:89|T4 (|shixudianlu:89|:14)
- 2 - B 11 AND2 0 3 1 0 |shixudianlu:89|T1 (|shixudianlu:89|:15)
- 7 - B 11 AND2 0 3 1 36 |shixudianlu:89|T2 (|shixudianlu:89|:17)
- 5 - B 11 AND2 0 2 1 0 |shixudianlu:89|T3 (|shixudianlu:89|:19)
- 1 - B 04 OR2 1 1 0 3 |shixudianlu:89|:25
- 2 - B 04 OR2 1 1 0 3 |shixudianlu:89|:26
- 5 - B 04 AND2 ! 1 0 0 2 |shixudianlu:89|:29
- 7 - B 04 OR2 ! 0 2 0 1 |shixudianlu:89|:30
- 8 - B 04 DFFE + 0 1 0 2 |shixudianlu:89|7474:32|1Q (|shixudianlu:89|7474:32|:9)
- 3 - B 04 DFFE 0 3 0 6 |shixudianlu:89|7474:33|1Q (|shixudianlu:89|7474:33|:9)
- 4 - B 11 DFFE 0 2 0 4 |shixudianlu:89|74175:13|4Q (|shixudianlu:89|74175:13|:13)
- 6 - B 11 DFFE 0 3 0 3 |shixudianlu:89|74175:13|3Q (|shixudianlu:89|74175:13|:14)
- 1 - B 11 DFFE 0 3 0 4 |shixudianlu:89|74175:13|2Q (|shixudianlu:89|74175:13|:15)
- 3 - B 11 AND2 0 3 0 8 :49
- 1 - C 08 OR2 s 0 4 0 1 |74244:9|~10~1~3~2
- 6 - C 08 OR2 0 3 1 25 |74244:9|~10~1~3
- 2 - C 15 OR2 s 0 4 0 1 |74244:9|~11~1~3~2
- 1 - A 04 OR2 0 3 1 10 |74244:9|~11~1~3
- 8 - A 23 OR2 ! 0 4 1 13 |74244:9|~31~1~3
- 5 - C 13 OR2 ! 0 4 1 15 |74244:9|~36~1~3
- 4 - A 06 DFFE 0 5 1 0 |74273:62|Q8 (|74273:62|:12)
- 8 - A 21 DFFE 0 5 1 0 |74273:62|Q7 (|74273:62|:13)
- 5 - A 02 DFFE 0 5 1 0 |74273:62|Q6 (|74273:62|:14)
- 5 - A 21 DFFE 0 5 1 0 |74273:62|Q5 (|74273:62|:15)
- 7 - A 05 DFFE 0 5 1 0 |74273:62|Q4 (|74273:62|:16)
- 4 - A 05 DFFE 0 5 1 0 |74273:62|Q3 (|74273:62|:17)
- 5 - A 06 DFFE 0 5 1 0 |74273:62|Q2 (|74273:62|:18)
- 5 - A 24 DFFE 0 5 1 0 |74273:62|Q1 (|74273:62|:19)
- 7 - A 01 DFFE 0 5 1 0 |74273:63|Q8 (|74273:63|:12)
- 1 - A 16 DFFE 0 5 1 0 |74273:63|Q7 (|74273:63|:13)
- 6 - A 01 DFFE 0 5 1 0 |74273:63|Q6 (|74273:63|:14)
- 8 - A 16 DFFE 0 5 1 0 |74273:63|Q5 (|74273:63|:15)
- 6 - A 12 DFFE 0 5 1 0 |74273:63|Q4 (|74273:63|:16)
- 3 - A 01 DFFE 0 5 1 0 |74273:63|Q3 (|74273:63|:17)
- 5 - A 20 DFFE 0 3 1 0 |74273:63|Q1 (|74273:63|:19)
- 1 - C 21 DFFE 1 1 0 1 |74273:64|Q8 (|74273:64|:12)
- 2 - C 21 DFFE 1 1 0 1 |74273:64|Q7 (|74273:64|:13)
- 1 - C 13 DFFE 1 1 0 1 |74273:64|Q6 (|74273:64|:14)
- 6 - C 21 DFFE 1 1 0 1 |74273:64|Q5 (|74273:64|:15)
- 1 - C 10 DFFE 1 1 1 1 |74273:64|Q4 (|74273:64|:16)
- 1 - C 15 DFFE 1 1 1 1 |74273:64|Q3 (|74273:64|:17)
- 8 - C 08 DFFE 1 1 1 1 |74273:64|Q2 (|74273:64|:18)
- 2 - A 04 DFFE 1 1 1 1 |74273:64|Q1 (|74273:64|:19)
- 3 - C 08 DFFE 0 2 1 8 |74273:65|Q8 (|74273:65|:12)
- 6 - A 23 DFFE 0 2 1 6 |74273:65|Q7 (|74273:65|:13)
- 7 - C 21 DFFE 0 2 1 4 |74273:65|Q6 (|74273:65|:14)
- 8 - B 11 DFFE 0 2 1 1 |74273:65|Q5 (|74273:65|:15)
- 2 - A 16 DFFE 0 5 1 0 |74273:65|Q4 (|74273:65|:16)
- 7 - A 16 DFFE 0 5 1 0 |74273:65|Q3 (|74273:65|:17)
- 8 - A 13 DFFE 0 5 1 0 |74273:65|Q2 (|74273:65|:18)
- 1 - A 20 DFFE 0 5 1 0 |74273:65|Q1 (|74273:65|:19)
- 8 - A 17 DFFE 0 4 1 0 |74273:66|Q1 (|74273:66|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\kongceshi2.rpt
kongceshi2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
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