📄 risel.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\risel.rpt
risel
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 8/ 96( 8%) 3/ 48( 6%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\risel.rpt
risel
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
LDRI : INPUT;
RI-BUS : INPUT;
SELRI : INPUT;
T2 : INPUT;
-- Node name is 'R1-BUS'
-- Equation name is 'R1-BUS', type is output
R1-BUS = !_LC7_B5;
-- Node name is 'R1LD'
-- Equation name is 'R1LD', type is output
R1LD = _LC3_B5;
-- Node name is 'R2-BUS'
-- Equation name is 'R2-BUS', type is output
R2-BUS = !_LC6_B5;
-- Node name is 'R2LD'
-- Equation name is 'R2LD', type is output
R2LD = _LC2_B5;
-- Node name is 'R3-BUS'
-- Equation name is 'R3-BUS', type is output
R3-BUS = !_LC1_B5;
-- Node name is 'R3LD'
-- Equation name is 'R3LD', type is output
R3LD = _LC4_B5;
-- Node name is 'R4-BUS'
-- Equation name is 'R4-BUS', type is output
R4-BUS = !_LC8_B5;
-- Node name is 'R4LD'
-- Equation name is 'R4LD', type is output
R4LD = _LC5_B5;
-- Node name is '|2sel1:17|:101' = '|2sel1:17|Y1'
-- Equation name is '_LC1_B9', type is buried
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ001);
_EQ001 = !D2 & !SELRI
# !D0 & !D2
# !D0 & SELRI;
-- Node name is '|2sel1:17|:102' = '|2sel1:17|Y2'
-- Equation name is '_LC2_B9', type is buried
!_LC2_B9 = _LC2_B9~NOT;
_LC2_B9~NOT = LCELL( _EQ002);
_EQ002 = !D1 & !D3
# !D1 & SELRI
# !D3 & !SELRI;
-- Node name is ':8'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ003);
_EQ003 = !_LC1_B9 & !_LC2_B9 & LDRI & T2;
-- Node name is ':9'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ004);
_EQ004 = _LC1_B9 & !_LC2_B9 & LDRI & T2;
-- Node name is ':10'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ005);
_EQ005 = !_LC1_B9 & _LC2_B9 & LDRI & T2;
-- Node name is ':11'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ006);
_EQ006 = _LC1_B9 & _LC2_B9 & LDRI & T2;
-- Node name is ':19'
-- Equation name is '_LC7_B5', type is buried
!_LC7_B5 = _LC7_B5~NOT;
_LC7_B5~NOT = LCELL( _EQ007);
_EQ007 = _LC2_B9
# _LC1_B9
# RI-BUS;
-- Node name is ':20'
-- Equation name is '_LC6_B5', type is buried
!_LC6_B5 = _LC6_B5~NOT;
_LC6_B5~NOT = LCELL( _EQ008);
_EQ008 = _LC2_B9
# !_LC1_B9
# RI-BUS;
-- Node name is ':21'
-- Equation name is '_LC1_B5', type is buried
!_LC1_B5 = _LC1_B5~NOT;
_LC1_B5~NOT = LCELL( _EQ009);
_EQ009 = RI-BUS
# !_LC2_B9
# _LC1_B9;
-- Node name is ':22'
-- Equation name is '_LC8_B5', type is buried
!_LC8_B5 = _LC8_B5~NOT;
_LC8_B5~NOT = LCELL( _EQ010);
_EQ010 = !_LC2_B9
# !_LC1_B9
# RI-BUS;
Project Information d:\computer\alu\risel.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,537K
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