yunsuan44.rpt

vhd语言

         #  _LC4_B14 &  _LC4_B18 &  _LC6_B13;

-- Node name is '|74244:30|~31~1~1~2' 
-- Equation name is '_LC4_B5', type is buried 
-- synthesized logic cell 
_LC4_B5  = LCELL( _EQ070);
  _EQ070 =  _LC6_B5 &  _LC7_B5
         # !_LC1_B21 &  _LC6_B5
         #  _LC7_B5 & !_LC8_B3
         # !_LC1_B21 & !_LC8_B3;

-- Node name is '|74244:30|~31~1~1~3' 
-- Equation name is '_LC4_B8', type is buried 
-- synthesized logic cell 
_LC4_B8  = LCELL( _EQ071);
  _EQ071 =  _LC5_B8 &  SW-BUS
         # !_LC4_B13 &  SW-BUS
         #  _LC5_B8 &  N5
         # !_LC4_B13 &  N5;

-- Node name is '|74244:30|~31~1~1~4' 
-- Equation name is '_LC2_B8', type is buried 
-- synthesized logic cell 
_LC2_B8  = LCELL( _EQ072);
  _EQ072 =  _LC4_B8 &  _LC8_B8
         # !_LC3_B13 &  _LC4_B8;

-- Node name is '|74244:30|~31~1~1' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = LCELL( _EQ073);
  _EQ073 =  ALU-BUS &  _LC2_B8 &  _LC4_B5
         #  _LC2_B8 &  _LC4_B5 &  _LC4_B6;

-- Node name is '|74244:30|~36~1~1~2' 
-- Equation name is '_LC2_B5', type is buried 
-- synthesized logic cell 
_LC2_B5  = LCELL( _EQ074);
  _EQ074 =  _LC1_B5 &  _LC5_B5
         #  _LC1_B5 & !_LC1_B21
         #  _LC5_B5 & !_LC8_B3
         # !_LC1_B21 & !_LC8_B3;

-- Node name is '|74244:30|~36~1~1~3' 
-- Equation name is '_LC3_B4', type is buried 
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ075);
  _EQ075 =  _LC4_B4 &  SW-BUS
         # !_LC4_B13 &  SW-BUS
         #  _LC4_B4 &  N4
         # !_LC4_B13 &  N4;

-- Node name is '|74244:30|~36~1~1~4' 
-- Equation name is '_LC2_B4', type is buried 
-- synthesized logic cell 
_LC2_B4  = LCELL( _EQ076);
  _EQ076 =  _LC3_B4 &  _LC6_B4
         #  _LC3_B4 & !_LC3_B13;

-- Node name is '|74244:30|~36~1~1' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = LCELL( _EQ077);
  _EQ077 =  ALU-BUS &  _LC2_B4 &  _LC2_B5
         #  _LC2_B4 &  _LC2_B5 &  _LC5_B11;

-- Node name is '|74273:22|:19' = '|74273:22|Q1' 
-- Equation name is '_LC2_B20', type is buried 
_LC2_B20 = DFFE( _LC1_B19,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:18' = '|74273:22|Q2' 
-- Equation name is '_LC7_B12', type is buried 
_LC7_B12 = DFFE( _LC8_B12,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:17' = '|74273:22|Q3' 
-- Equation name is '_LC8_B7', type is buried 
_LC8_B7  = DFFE( _LC1_B7,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:16' = '|74273:22|Q4' 
-- Equation name is '_LC6_B17', type is buried 
_LC6_B17 = DFFE( _LC5_B17,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:15' = '|74273:22|Q5' 
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = DFFE( _LC4_B11,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:14' = '|74273:22|Q6' 
-- Equation name is '_LC7_B6', type is buried 
_LC7_B6  = DFFE( _LC5_B6,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:13' = '|74273:22|Q7' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = DFFE( _LC6_B14,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:22|:12' = '|74273:22|Q8' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = DFFE( _LC1_B14,  _LC2_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:19' = '|74273:23|Q1' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = DFFE( _LC1_B19,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:18' = '|74273:23|Q2' 
-- Equation name is '_LC6_B12', type is buried 
_LC6_B12 = DFFE( _LC8_B12,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:17' = '|74273:23|Q3' 
-- Equation name is '_LC7_B7', type is buried 
_LC7_B7  = DFFE( _LC1_B7,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:16' = '|74273:23|Q4' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = DFFE( _LC5_B17,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:15' = '|74273:23|Q5' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _LC4_B11,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:14' = '|74273:23|Q6' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = DFFE( _LC5_B6,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:13' = '|74273:23|Q7' 
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = DFFE( _LC6_B14,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74273:23|:12' = '|74273:23|Q8' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = DFFE( _LC1_B14,  _LC6_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:13' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = DFFE( _LC1_B19,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:14' 
-- Equation name is '_LC7_B8', type is buried 
_LC7_B8  = DFFE( _LC8_B12,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:15' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = DFFE( _LC1_B7,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:16' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = DFFE( _LC5_B17,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:17' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = DFFE( _LC4_B11,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:18' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = DFFE( _LC5_B6,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:19' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = DFFE( _LC6_B14,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:24|:20' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = DFFE( _LC1_B14,  _LC7_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:13' 
-- Equation name is '_LC8_B19', type is buried 
_LC8_B19 = DFFE( _LC1_B19,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:14' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = DFFE( _LC8_B12,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:15' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = DFFE( _LC1_B7,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:16' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = DFFE( _LC5_B17,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:17' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = DFFE( _LC4_B11,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:18' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = DFFE( _LC5_B6,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:19' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = DFFE( _LC6_B14,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:25|:20' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = DFFE( _LC1_B14,  _LC5_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:13' 
-- Equation name is '_LC7_B19', type is buried 
_LC7_B19 = DFFE( _LC1_B19,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:14' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = DFFE( _LC8_B12,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:15' 
-- Equation name is '_LC3_B3', type is buried 
_LC3_B3  = DFFE( _LC1_B7,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:16' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = DFFE( _LC5_B17,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:17' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = DFFE( _LC4_B11,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:18' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = DFFE( _LC5_B6,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:19' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = DFFE( _LC6_B14,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:26|:20' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = DFFE( _LC1_B14,  _LC5_B21,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:13' 
-- Equation name is '_LC7_B22', type is buried 
_LC7_B22 = DFFE( _LC1_B19,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:14' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = DFFE( _LC8_B12,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:15' 
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = DFFE( _LC1_B7,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:16' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = DFFE( _LC5_B17,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:17' 
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = DFFE( _LC4_B11,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:18' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = DFFE( _LC5_B6,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:19' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = DFFE( _LC6_B14,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is '|74374:27|:20' 
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = DFFE( _LC1_B14,  _LC4_B19,  VCC,  VCC,  VCC);

-- Node name is ':18' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = LCELL( _EQ078);
  _EQ078 =  LDDR2 &  T2;

-- Node name is ':19' 
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = LCELL( _EQ079);
  _EQ079 =  LDDR1 &  T2;



Project Information                              d:\computer\alu\yunsuan44.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 29,063K