📄 yunsuan44.rpt
字号:
- 2 - B 13 OR2 s 0 4 0 1 |74244:30|~11~1~1~4
- 5 - B 17 OR2 1 3 1 6 |74244:30|~11~1~1
- 5 - B 03 OR2 s 0 4 0 1 |74244:30|~26~1~1~2
- 1 - B 10 OR2 s 2 2 0 1 |74244:30|~26~1~1~3
- 1 - B 03 OR2 s 0 4 0 1 |74244:30|~26~1~1~4
- 1 - B 14 OR2 1 3 1 6 |74244:30|~26~1~1
- 3 - B 18 OR2 s 2 2 0 1 |74244:30|~27~1~1~2
- 4 - B 18 OR2 s 0 3 0 1 |74244:30|~27~1~1~3
- 6 - B 13 OR2 s 0 4 0 1 |74244:30|~27~1~1~4
- 6 - B 14 OR2 1 3 1 6 |74244:30|~27~1~1
- 4 - B 05 OR2 s 0 4 0 1 |74244:30|~31~1~1~2
- 4 - B 08 OR2 s 2 2 0 1 |74244:30|~31~1~1~3
- 2 - B 08 OR2 s 0 3 0 1 |74244:30|~31~1~1~4
- 5 - B 06 OR2 1 3 1 6 |74244:30|~31~1~1
- 2 - B 05 OR2 s 0 4 0 1 |74244:30|~36~1~1~2
- 3 - B 04 OR2 s 2 2 0 1 |74244:30|~36~1~1~3
- 2 - B 04 OR2 s 0 3 0 1 |74244:30|~36~1~1~4
- 4 - B 11 OR2 1 3 1 6 |74244:30|~36~1~1
- 8 - B 20 DFFE 0 2 0 2 |74273:22|Q8 (|74273:22|:12)
- 8 - B 14 DFFE 0 2 0 2 |74273:22|Q7 (|74273:22|:13)
- 7 - B 06 DFFE 0 2 0 2 |74273:22|Q6 (|74273:22|:14)
- 7 - B 11 DFFE 0 2 0 2 |74273:22|Q5 (|74273:22|:15)
- 6 - B 17 DFFE 0 2 0 2 |74273:22|Q4 (|74273:22|:16)
- 8 - B 07 DFFE 0 2 0 2 |74273:22|Q3 (|74273:22|:17)
- 7 - B 12 DFFE 0 2 0 2 |74273:22|Q2 (|74273:22|:18)
- 2 - B 20 DFFE 0 2 0 2 |74273:22|Q1 (|74273:22|:19)
- 2 - B 10 DFFE 0 2 0 1 |74273:23|Q8 (|74273:23|:12)
- 7 - B 14 DFFE 0 2 0 2 |74273:23|Q7 (|74273:23|:13)
- 6 - B 06 DFFE 0 2 0 2 |74273:23|Q6 (|74273:23|:14)
- 6 - B 11 DFFE 0 2 0 2 |74273:23|Q5 (|74273:23|:15)
- 4 - B 17 DFFE 0 2 0 2 |74273:23|Q4 (|74273:23|:16)
- 7 - B 07 DFFE 0 2 0 2 |74273:23|Q3 (|74273:23|:17)
- 6 - B 12 DFFE 0 2 0 2 |74273:23|Q2 (|74273:23|:18)
- 1 - B 20 DFFE 0 2 0 2 |74273:23|Q1 (|74273:23|:19)
- 6 - B 22 DFFE 0 2 0 1 |74374:24|:13
- 7 - B 08 DFFE 0 2 0 1 |74374:24|:14
- 8 - B 04 DFFE 0 2 0 1 |74374:24|:15
- 5 - B 13 DFFE 0 2 0 1 |74374:24|:16
- 6 - B 04 DFFE 0 2 0 1 |74374:24|:17
- 8 - B 08 DFFE 0 2 0 1 |74374:24|:18
- 8 - B 13 DFFE 0 2 0 1 |74374:24|:19
- 1 - B 04 DFFE 0 2 0 1 |74374:24|:20
- 8 - B 19 DFFE 0 2 0 1 |74374:25|:13
- 6 - B 08 DFFE 0 2 0 1 |74374:25|:14
- 7 - B 04 DFFE 0 2 0 1 |74374:25|:15
- 1 - B 13 DFFE 0 2 0 1 |74374:25|:16
- 4 - B 04 DFFE 0 2 0 1 |74374:25|:17
- 5 - B 08 DFFE 0 2 0 1 |74374:25|:18
- 7 - B 13 DFFE 0 2 0 1 |74374:25|:19
- 3 - B 10 DFFE 0 2 0 1 |74374:25|:20
- 7 - B 19 DFFE 0 2 0 1 |74374:26|:13
- 3 - B 05 DFFE 0 2 0 1 |74374:26|:14
- 3 - B 03 DFFE 0 2 0 1 |74374:26|:15
- 7 - B 18 DFFE 0 2 0 1 |74374:26|:16
- 5 - B 05 DFFE 0 2 0 1 |74374:26|:17
- 7 - B 05 DFFE 0 2 0 1 |74374:26|:18
- 8 - B 18 DFFE 0 2 0 1 |74374:26|:19
- 7 - B 03 DFFE 0 2 0 1 |74374:26|:20
- 7 - B 22 DFFE 0 2 0 1 |74374:27|:13
- 8 - B 05 DFFE 0 2 0 1 |74374:27|:14
- 2 - B 03 DFFE 0 2 0 1 |74374:27|:15
- 2 - B 18 DFFE 0 2 0 1 |74374:27|:16
- 1 - B 05 DFFE 0 2 0 1 |74374:27|:17
- 6 - B 05 DFFE 0 2 0 1 |74374:27|:18
- 6 - B 18 DFFE 0 2 0 1 |74374:27|:19
- 6 - B 03 DFFE 0 2 0 1 |74374:27|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\yunsuan44.rpt
yunsuan44
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 29/ 96( 30%) 21/ 48( 43%) 24/ 48( 50%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\yunsuan44.rpt
yunsuan44
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 |risel:1|R1LD
LCELL 8 |risel:1|R2LD
LCELL 8 |risel:1|R3LD
LCELL 8 |risel:1|R4LD
LCELL 8 :18
LCELL 8 :19
Device-Specific Information: d:\computer\alu\yunsuan44.rpt
yunsuan44
** EQUATIONS **
ALU-BUS : INPUT;
CN : INPUT;
DR0 : INPUT;
DR1 : INPUT;
DR2 : INPUT;
DR3 : INPUT;
LDDR1 : INPUT;
LDDR2 : INPUT;
LDRI : INPUT;
M : INPUT;
N0 : INPUT;
N1 : INPUT;
N2 : INPUT;
N3 : INPUT;
N4 : INPUT;
N5 : INPUT;
N6 : INPUT;
N7 : INPUT;
RI-BUS : INPUT;
SELRI : INPUT;
SW-BUS : INPUT;
S0 : INPUT;
S1 : INPUT;
S2 : INPUT;
S3 : INPUT;
T2 : INPUT;
-- Node name is 'BUS0'
-- Equation name is 'BUS0', type is output
BUS0 = _LC1_B19;
-- Node name is 'BUS1'
-- Equation name is 'BUS1', type is output
BUS1 = _LC8_B12;
-- Node name is 'BUS2'
-- Equation name is 'BUS2', type is output
BUS2 = _LC1_B7;
-- Node name is 'BUS3'
-- Equation name is 'BUS3', type is output
BUS3 = _LC5_B17;
-- Node name is 'BUS4'
-- Equation name is 'BUS4', type is output
BUS4 = _LC4_B11;
-- Node name is 'BUS5'
-- Equation name is 'BUS5', type is output
BUS5 = _LC5_B6;
-- Node name is 'BUS6'
-- Equation name is 'BUS6', type is output
BUS6 = _LC6_B14;
-- Node name is 'BUS7'
-- Equation name is 'BUS7', type is output
BUS7 = _LC1_B14;
-- Node name is '|risel:1|:8' = '|risel:1|R1LD'
-- Equation name is '_LC4_B19', type is buried
_LC4_B19 = LCELL( _EQ001);
_EQ001 = !_LC3_B21 & LDRI & T2;
-- Node name is '|risel:1|:9' = '|risel:1|R2LD'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ002);
_EQ002 = !_LC6_B21 & LDRI & T2;
-- Node name is '|risel:1|:10' = '|risel:1|R3LD'
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = LCELL( _EQ003);
_EQ003 = !_LC8_B21 & LDRI & T2;
-- Node name is '|risel:1|:11' = '|risel:1|R4LD'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ004);
_EQ004 = !_LC4_B21 & LDRI & T2;
-- Node name is '|risel:1|2sel1:17|:101' = '|risel:1|2sel1:17|Y1'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ005);
_EQ005 = DR1 & !SELRI
# DR0 & SELRI;
-- Node name is '|risel:1|4sel1:12|:6'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ006);
_EQ006 = DR3 & !SELRI
# DR2 & SELRI
# _LC2_B21;
-- Node name is '|risel:1|4sel1:12|:7'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ007);
_EQ007 = DR3 & !SELRI
# DR2 & SELRI
# !_LC2_B21;
-- Node name is '|risel:1|4sel1:12|:8'
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = LCELL( _EQ008);
_EQ008 = _LC2_B21
# !DR3 & !SELRI
# !DR2 & SELRI
# !DR2 & !DR3;
-- Node name is '|risel:1|4sel1:12|:9'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ009);
_EQ009 = !DR3 & !SELRI
# !DR2 & SELRI
# !DR2 & !DR3
# !_LC2_B21;
-- Node name is '|risel:1|:19'
-- Equation name is '_LC8_B3', type is buried
!_LC8_B3 = _LC8_B3~NOT;
_LC8_B3~NOT = LCELL( _EQ010);
_EQ010 = RI-BUS
# _LC3_B21;
-- Node name is '|risel:1|:20'
-- Equation name is '_LC1_B21', type is buried
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL( _EQ011);
_EQ011 = RI-BUS
# _LC6_B21;
-- Node name is '|risel:1|:21'
-- Equation name is '_LC4_B13', type is buried
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ012);
_EQ012 = RI-BUS
# _LC8_B21;
-- Node name is '|risel:1|:22'
-- Equation name is '_LC3_B13', type is buried
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ013);
_EQ013 = RI-BUS
# _LC4_B21;
-- Node name is '|74181:20|:43'
-- Equation name is '_LC1_B11', type is buried
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ014);
_EQ014 = _LC6_B11
# !_LC7_B11 & S1
# _LC7_B11 & S0;
-- Node name is '|74181:20|:44'
-- Equation name is '_LC2_B6', type is buried
!_LC2_B6 = _LC2_B6~NOT;
_LC2_B6~NOT = LCELL( _EQ015);
_EQ015 = _LC6_B6
# !_LC7_B6 & S1
# _LC7_B6 & S0;
-- Node name is '|74181:20|:45'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ016);
_EQ016 = !_LC7_B14 & !S0 & !S1
# !_LC7_B14 & _LC8_B14 & !S0
# !_LC7_B14 & !_LC8_B14 & !S1;
-- Node name is '|74181:20|:46'
-- Equation name is '_LC2_B11', type is buried
!_LC2_B11 = _LC2_B11~NOT;
_LC2_B11~NOT = LCELL( _EQ017);
_EQ017 = _LC6_B11 & !_LC7_B11 & S2
# _LC6_B11 & _LC7_B11 & S3;
-- Node name is '|74181:20|:47'
-- Equation name is '_LC3_B6', type is buried
!_LC3_B6 = _LC3_B6~NOT;
_LC3_B6~NOT = LCELL( _EQ018);
_EQ018 = _LC6_B6 & !_LC7_B6 & S2
# _LC6_B6 & _LC7_B6 & S3;
-- Node name is '|74181:20|:48'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ019);
_EQ019 = !_LC7_B14
# !S2 & !S3
# _LC8_B14 & !S3
# !_LC8_B14 & !S2;
-- Node name is '|74181:20|~51~1'
-- Equation name is '_LC6_B20', type is buried
-- synthesized logic cell
_LC6_B20 = LCELL( _EQ020);
_EQ020 = !_LC8_B20 & !S1
# _LC8_B20 & !S0
# !S0 & !S1;
-- Node name is '|74181:20|~52~1'
-- Equation name is '_LC5_B20', type is buried
-- synthesized logic cell
_LC5_B20 = LCELL( _EQ021);
_EQ021 = !_LC8_B20 & !S2
# _LC8_B20 & !S3
# !S2 & !S3;
-- Node name is '|74181:20|~74~1'
-- Equation name is '_LC3_B11', type is buried
-- synthesized logic cell
_LC3_B11 = LCELL( _EQ022);
_EQ022 = !_LC1_B11 & !_LC8_B17
# !_LC1_B11 & !_LC2_B11;
-- Node name is '|74181:20|~74~2'
-- Equation name is '_LC1_B6', type is buried
-- synthesized logic cell
_LC1_B6 = LCELL( _EQ023);
_EQ023 = !_LC2_B6 & _LC3_B11
# !_LC2_B6 & !_LC3_B6;
-- Node name is '|74181:20|:74'
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