📄 cdu.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\cdu.rpt
cdu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\cdu.rpt
cdu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CDUCLK
Device-Specific Information: d:\computer\alu\cdu.rpt
cdu
** EQUATIONS **
CDUCLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC4_C15;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC3_C15;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC5_C15;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC7_A18;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC4_A18;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC1_A18;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = _LC8_A18;
-- Node name is 'Q8'
-- Equation name is 'Q8', type is output
Q8 = _LC2_A18;
-- Node name is '|cdu16:20|74163:1|f74163:sub|:34' = '|cdu16:20|74163:1|f74163:sub|QA'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = DFFE( _EQ001, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ001 = CLR & _LC4_A18 & !_LC7_A18
# CLR & !_LC1_C15 & _LC4_A18
# CLR & _LC1_C15 & !_LC4_A18 & _LC7_A18;
-- Node name is '|cdu16:20|74163:1|f74163:sub|:111' = '|cdu16:20|74163:1|f74163:sub|QB'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ002, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ002 = CLR & _LC1_A18 & !_LC4_A18
# CLR & _LC1_A18 & !_LC5_A18
# CLR & !_LC1_A18 & _LC4_A18 & _LC5_A18;
-- Node name is '|cdu16:20|74163:1|f74163:sub|:122' = '|cdu16:20|74163:1|f74163:sub|QC'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = DFFE( _EQ003, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ003 = CLR & !_LC3_A18 & _LC8_A18
# CLR & _LC3_A18 & !_LC8_A18;
-- Node name is '|cdu16:20|74163:1|f74163:sub|:134' = '|cdu16:20|74163:1|f74163:sub|QD'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( _EQ004, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ004 = CLR & _LC2_A18 & !_LC8_A18
# CLR & _LC2_A18 & !_LC3_A18
# CLR & !_LC2_A18 & _LC3_A18 & _LC8_A18;
-- Node name is '|cdu16:20|74163:1|f74163:sub|:119'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ005);
_EQ005 = _LC1_A18 & _LC1_C15 & _LC4_A18 & _LC7_A18;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:34' = '|cdu16:22|74163:1|f74163:sub|QA'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = DFFE( _EQ006, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ006 = CLR & !EN & _LC4_C15
# CLR & EN & !_LC4_C15;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:111' = '|cdu16:22|74163:1|f74163:sub|QB'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = DFFE( _EQ007, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ007 = CLR & _LC3_C15 & !_LC4_C15
# CLR & !EN & _LC3_C15
# CLR & EN & !_LC3_C15 & _LC4_C15;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:122' = '|cdu16:22|74163:1|f74163:sub|QC'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = DFFE( _EQ008, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ008 = CLR & !_LC2_C15 & _LC5_C15
# CLR & !EN & _LC5_C15
# CLR & EN & _LC2_C15 & !_LC5_C15;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:134' = '|cdu16:22|74163:1|f74163:sub|QD'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = DFFE( _EQ009, GLOBAL( CDUCLK), VCC, VCC, VCC);
_EQ009 = CLR & !_LC1_C15 & _LC7_A18
# CLR & !EN & _LC7_A18
# CLR & EN & _LC1_C15 & !_LC7_A18;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:106'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ010);
_EQ010 = EN & _LC3_C15 & _LC4_C15;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:117'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = LCELL( _EQ011);
_EQ011 = EN & _LC3_C15 & _LC4_C15 & _LC5_C15;
-- Node name is '|cdu16:22|74163:1|f74163:sub|:128'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ012);
_EQ012 = _LC1_C15 & _LC7_A18;
Project Information d:\computer\alu\cdu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,344K
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