📄 yunsuan11.rpt
字号:
- 1 - B 09 OR2 2 2 0 2 |74181:11|:51
- 2 - B 09 OR2 2 2 0 2 |74181:11|:52
- 6 - B 20 OR2 s 0 3 0 2 |74181:11|~75~1
- 6 - B 09 OR2 1 3 0 1 |74181:11|:77
- 1 - B 17 OR2 s 1 2 0 2 |74181:11|CN4~1 (|74181:11|~78~1)
- 4 - B 21 OR2 s 0 3 0 2 |74181:11|CN4~2 (|74181:11|~78~2)
- 4 - B 09 OR2 ! 0 3 0 2 |74181:11|CN4 (|74181:11|:78)
- 5 - B 17 OR2 2 2 0 1 |74181:11|:80
- 7 - B 20 OR2 1 3 0 1 |74181:11|:81
- 5 - B 21 OR2 1 3 0 1 |74181:11|:82
- 7 - B 09 OR2 ! 2 2 0 2 |74181:13|:43
- 3 - B 02 OR2 2 2 0 2 |74181:13|:44
- 3 - B 13 OR2 2 2 0 2 |74181:13|:45
- 8 - B 09 OR2 ! 2 2 0 2 |74181:13|:46
- 5 - B 02 OR2 2 2 0 2 |74181:13|:47
- 1 - B 13 OR2 2 2 0 2 |74181:13|:48
- 4 - B 13 OR2 s 2 1 0 1 |74181:13|~51~1
- 6 - B 13 OR2 s 2 1 0 1 |74181:13|~52~1
- 5 - B 13 OR2 1 3 0 1 |74181:13|:74
- 8 - B 02 OR2 s 0 3 0 2 |74181:13|~75~1
- 7 - B 13 OR2 0 4 0 1 |74181:13|:77
- 5 - B 09 OR2 s 0 3 0 2 |74181:13|~79~1
- 3 - B 09 OR2 1 3 0 1 |74181:13|:80
- 7 - B 02 OR2 1 3 0 1 |74181:13|:81
- 2 - B 13 OR2 1 3 0 1 |74181:13|:82
- 2 - A 14 OR2 s 0 4 0 1 |74244:1|~1~1~1~2
- 5 - A 14 OR2 s 1 3 0 1 |74244:1|~1~1~1~3
- 3 - B 17 OR2 s 2 2 0 1 |74244:1|~1~1~1~4
- 4 - B 17 OR2 s 0 4 0 1 |74244:1|~1~1~1~5
- 3 - A 14 OR2 1 3 1 9 |74244:1|~1~1~1
- 5 - A 19 OR2 s 2 2 0 1 |74244:1|~6~1~1~2
- 4 - A 22 OR2 s 1 3 0 1 |74244:1|~6~1~1~3
- 5 - A 22 OR2 s 1 3 0 1 |74244:1|~6~1~1~4
- 6 - A 22 OR2 s 0 4 0 1 |74244:1|~6~1~1~5
- 3 - A 22 OR2 1 3 1 9 |74244:1|~6~1~1
- 4 - A 19 OR2 s 2 2 0 1 |74244:1|~10~1~1~2
- 4 - A 24 OR2 s 0 3 0 1 |74244:1|~10~1~1~3
- 5 - A 24 OR2 s 0 3 0 1 |74244:1|~10~1~1~4
- 6 - A 24 OR2 s 0 4 0 1 |74244:1|~10~1~1~5
- 2 - A 24 OR2 1 3 1 9 |74244:1|~10~1~1
- 2 - A 17 OR2 s 2 2 0 1 |74244:1|~11~1~1~2
- 3 - A 17 OR2 s 0 3 0 1 |74244:1|~11~1~1~3
- 5 - A 17 OR2 s 0 3 0 1 |74244:1|~11~1~1~4
- 6 - A 17 OR2 s 0 4 0 1 |74244:1|~11~1~1~5
- 4 - A 17 OR2 1 3 1 9 |74244:1|~11~1~1
- 3 - A 21 OR2 s 2 2 0 1 |74244:1|~26~1~1~2
- 4 - A 21 OR2 s 1 3 0 1 |74244:1|~26~1~1~3
- 5 - A 21 OR2 s 1 3 0 1 |74244:1|~26~1~1~4
- 6 - A 21 OR2 s 0 4 0 1 |74244:1|~26~1~1~5
- 1 - A 21 OR2 1 3 1 9 |74244:1|~26~1~1
- 3 - A 20 OR2 s 2 2 0 1 |74244:1|~27~1~1~2
- 4 - A 20 OR2 s 0 3 0 1 |74244:1|~27~1~1~3
- 3 - A 15 OR2 s 0 3 0 1 |74244:1|~27~1~1~4
- 4 - A 15 OR2 s 0 4 0 1 |74244:1|~27~1~1~5
- 5 - A 15 OR2 1 3 1 9 |74244:1|~27~1~1
- 3 - A 04 OR2 s 2 2 0 1 |74244:1|~31~1~1~2
- 4 - A 04 OR2 s 0 3 0 1 |74244:1|~31~1~1~3
- 5 - A 04 OR2 s 0 3 0 1 |74244:1|~31~1~1~4
- 6 - A 04 OR2 s 0 4 0 1 |74244:1|~31~1~1~5
- 1 - A 04 OR2 1 3 1 9 |74244:1|~31~1~1
- 1 - A 11 OR2 s 2 2 0 1 |74244:1|~36~1~1~2
- 3 - A 09 OR2 s 0 3 0 1 |74244:1|~36~1~1~3
- 5 - A 09 OR2 s 0 3 0 1 |74244:1|~36~1~1~4
- 6 - A 09 OR2 s 0 4 0 1 |74244:1|~36~1~1~5
- 4 - A 09 OR2 1 3 1 9 |74244:1|~36~1~1
- 7 - B 17 OR2 2 2 0 1 |74244:15|~1~1
- 3 - B 20 OR2 2 2 0 1 |74244:15|~6~1
- 1 - A 24 OR2 2 2 0 1 |74244:15|~10~1
- 8 - B 04 OR2 2 2 0 1 |74244:15|~11~1
- 8 - B 13 OR2 2 2 0 1 |74244:15|~26~1
- 1 - A 15 OR2 2 2 0 1 |74244:15|~27~1
- 4 - B 02 OR2 2 2 0 1 |74244:15|~31~1
- 1 - A 09 OR2 2 2 0 1 |74244:15|~36~1
- 4 - B 18 DFFE 0 2 0 8 |74273:7|Q8 (|74273:7|:12)
- 4 - B 24 DFFE 0 2 0 3 |74273:7|Q7 (|74273:7|:13)
- 1 - B 02 DFFE 0 2 0 4 |74273:7|Q6 (|74273:7|:14)
- 1 - B 03 DFFE 0 2 0 5 |74273:7|Q5 (|74273:7|:15)
- 2 - B 19 DFFE 0 2 0 6 |74273:7|Q4 (|74273:7|:16)
- 8 - B 21 DFFE 0 2 0 4 |74273:7|Q3 (|74273:7|:17)
- 5 - B 14 DFFE 0 2 0 5 |74273:7|Q2 (|74273:7|:18)
- 5 - B 15 DFFE 0 2 0 18 |74273:7|Q1 (|74273:7|:19)
- 1 - B 16 DFFE 0 2 0 11 |74273:10|Q8 (|74273:10|:12)
- 5 - B 16 DFFE 0 2 0 3 |74273:10|Q7 (|74273:10|:13)
- 7 - B 16 DFFE 0 2 0 4 |74273:10|Q6 (|74273:10|:14)
- 2 - B 16 DFFE 0 2 0 7 |74273:10|Q5 (|74273:10|:15)
- 4 - B 16 DFFE 0 2 0 5 |74273:10|Q4 (|74273:10|:16)
- 3 - B 16 DFFE 0 2 0 4 |74273:10|Q3 (|74273:10|:17)
- 6 - B 16 DFFE 0 2 0 5 |74273:10|Q2 (|74273:10|:18)
- 8 - B 16 DFFE 0 2 0 17 |74273:10|Q1 (|74273:10|:19)
- 5 - A 03 DFFE 0 2 0 1 |74273:83|Q8 (|74273:83|:12)
- 5 - A 07 DFFE 0 2 0 1 |74273:83|Q7 (|74273:83|:13)
- 8 - A 01 DFFE 0 2 0 1 |74273:83|Q6 (|74273:83|:14)
- 7 - A 01 DFFE 0 2 0 1 |74273:83|Q5 (|74273:83|:15)
- 5 - A 01 DFFE 0 2 0 1 |74273:83|Q4 (|74273:83|:16)
- 2 - A 07 DFFE 0 2 0 1 |74273:83|Q3 (|74273:83|:17)
- 1 - A 07 DFFE 0 2 0 1 |74273:83|Q2 (|74273:83|:18)
- 4 - A 03 DFFE 0 2 0 1 |74273:83|Q1 (|74273:83|:19)
- 6 - A 03 LCELL 0 1 1 8 |74373:97|:12
- 3 - A 07 LCELL 0 1 1 8 |74373:97|:13
- 8 - A 07 LCELL 0 1 1 8 |74373:97|:14
- 2 - A 01 LCELL 0 1 1 8 |74373:97|:15
- 6 - A 01 LCELL 0 1 1 8 |74373:97|:16
- 4 - A 01 LCELL 0 1 1 8 |74373:97|:17
- 4 - A 07 LCELL 0 1 1 8 |74373:97|:18
- 1 - A 03 LCELL 0 1 1 8 |74373:97|:19
- 8 - B 17 DFFE 0 2 0 1 |74374:2|:13
- 8 - A 16 DFFE 0 2 0 1 |74374:2|:14
- 1 - A 16 DFFE 0 2 0 1 |74374:2|:15
- 4 - A 16 DFFE 0 2 0 1 |74374:2|:16
- 1 - A 08 DFFE 0 2 0 1 |74374:2|:17
- 1 - A 10 DFFE 0 2 0 1 |74374:2|:18
- 5 - A 20 DFFE 0 2 0 1 |74374:2|:19
- 5 - A 16 DFFE 0 2 0 1 |74374:2|:20
- 1 - A 18 DFFE 0 2 0 1 |74374:4|:13
- 7 - A 22 DFFE 0 2 0 1 |74374:4|:14
- 7 - A 24 DFFE 0 2 0 1 |74374:4|:15
- 7 - A 17 DFFE 0 2 0 1 |74374:4|:16
- 7 - A 09 DFFE 0 2 0 1 |74374:4|:17
- 7 - A 04 DFFE 0 2 0 1 |74374:4|:18
- 6 - A 15 DFFE 0 2 0 1 |74374:4|:19
- 7 - A 21 DFFE 0 2 0 1 |74374:4|:20
- 1 - A 22 OR2 1 2 0 1 |74374:4|~41~1
- 3 - A 24 OR2 1 2 0 1 |74374:4|~42~1
- 1 - A 17 OR2 1 2 0 1 |74374:4|~43~1
- 2 - A 09 OR2 1 2 0 1 |74374:4|~44~1
- 2 - A 04 OR2 1 2 0 1 |74374:4|~45~1
- 2 - A 15 OR2 1 2 0 1 |74374:4|~46~1
- 2 - A 21 OR2 1 2 0 1 |74374:4|~47~1
- 6 - A 14 DFFE 0 2 0 1 |74374:5|:13
- 2 - A 16 DFFE 0 2 0 1 |74374:5|:14
- 3 - A 16 DFFE 0 2 0 1 |74374:5|:15
- 6 - A 16 DFFE 0 2 0 1 |74374:5|:16
- 1 - A 01 DFFE 0 2 0 1 |74374:5|:17
- 3 - A 01 DFFE 0 2 0 1 |74374:5|:18
- 1 - A 05 DFFE 0 2 0 1 |74374:5|:19
- 7 - A 16 DFFE 0 2 0 1 |74374:5|:20
- 7 - A 14 DFFE 0 2 0 1 |74374:6|:13
- 8 - A 22 DFFE 0 2 0 1 |74374:6|:14
- 8 - A 24 DFFE 0 2 0 1 |74374:6|:15
- 8 - A 17 DFFE 0 2 0 1 |74374:6|:16
- 8 - A 09 DFFE 0 2 0 1 |74374:6|:17
- 8 - A 04 DFFE 0 2 0 1 |74374:6|:18
- 7 - A 15 DFFE 0 2 0 1 |74374:6|:19
- 8 - A 21 DFFE 0 2 0 1 |74374:6|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 42/ 96( 43%) 20/ 48( 41%) 36/ 48( 75%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
B: 38/ 96( 39%) 39/ 48( 81%) 21/ 48( 43%) 6/16( 37%) 1/16( 6%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 7/24( 29%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
14: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 4/24( 16%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
23: 5/24( 20%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 CLK-CDU
LCELL 8 |risel:121|R1LD
LCELL 8 |risel:121|R2LD
LCELL 8 |risel:121|R3LD
LCELL 8 |risel:121|R4LD
LCELL 8 :24
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