📄 yunsuan11.rpt
字号:
51 - - - 14 INPUT 0 0 0 1 LDDR1
142 - - - 24 INPUT 0 0 0 1 LDDR2
49 - - - 14 INPUT 0 0 0 4 LDRI
97 - - B -- INPUT 0 0 0 8 M
125 - - - -- INPUT 0 0 0 8 MUL
122 - - - 13 INPUT 0 0 0 8 PC-BUS
56 - - - -- INPUT 0 0 0 9 RD
124 - - - -- INPUT 0 0 0 15 RI-BUS
140 - - - 22 INPUT 0 0 0 5 SELRI
130 - - - 15 INPUT 0 0 0 8 SW-BUS
10 - - B -- INPUT 0 0 0 8 S0
95 - - B -- INPUT 0 0 0 8 S1
9 - - B -- INPUT 0 0 0 8 S2
96 - - B -- INPUT 0 0 0 8 S3
41 - - - 20 INPUT 0 0 0 6 T2
63 - - - 10 INPUT 0 0 0 2 T3
14 - - C -- INPUT 0 0 0 1 WE
54 - - - -- INPUT G 0 0 0 0 161CLRN
8 - - A -- INPUT 0 0 0 8 161LOAD
120 - - - 08 INPUT 0 0 0 1 161PC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
113 - - - 03 OUTPUT 0 1 0 0 ADR0
102 - - A -- OUTPUT 0 1 0 0 ADR1
67 - - - 08 OUTPUT 0 1 0 0 ADR2
110 - - - 01 OUTPUT 0 1 0 0 ADR3
100 - - A -- OUTPUT 0 1 0 0 ADR4
101 - - A -- OUTPUT 0 1 0 0 ADR5
68 - - - 07 OUTPUT 0 1 0 0 ADR6
109 - - A -- OUTPUT 0 1 0 0 ADR7
128 - - - 13 OUTPUT 0 1 0 0 BUS0
138 - - - 21 OUTPUT 0 1 0 0 BUS1
141 - - - 23 OUTPUT 0 1 0 0 BUS2
133 - - - 18 OUTPUT 0 1 0 0 BUS3
88 - - D -- OUTPUT 0 1 0 0 BUS4
72 - - - 03 OUTPUT 0 1 0 0 BUS5
131 - - - 16 OUTPUT 0 1 0 0 BUS6
39 - - - 21 OUTPUT 0 1 0 0 BUS7
98 - - B -- OUTPUT 0 1 0 0 N0
36 - - - 24 OUTPUT 0 1 0 0 N1
27 - - E -- OUTPUT 0 1 0 0 N2
21 - - D -- OUTPUT 0 1 0 0 N3
42 - - - 19 OUTPUT 0 1 0 0 N4
7 - - A -- OUTPUT 0 1 0 0 N5
135 - - - 19 OUTPUT 0 1 0 0 N6
143 - - A -- OUTPUT 0 1 0 0 N7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 21 OR2 0 3 0 11 |bumaqi:140|buyuanyima:2|74157:26|Y2 (|bumaqi:140|buyuanyima:2|74157:26|:23)
- 1 - B 21 OR2 0 4 0 9 |bumaqi:140|buyuanyima:2|74157:26|Y3 (|bumaqi:140|buyuanyima:2|74157:26|:24)
- 1 - B 05 OR2 0 3 0 5 |bumaqi:140|buyuanyima:2|74157:26|Y4 (|bumaqi:140|buyuanyima:2|74157:26|:25)
- 6 - B 05 OR2 0 4 0 3 |bumaqi:140|buyuanyima:2|74157:27|Y1 (|bumaqi:140|buyuanyima:2|74157:27|:22)
- 6 - B 02 OR2 0 4 0 3 |bumaqi:140|buyuanyima:2|74157:27|Y2 (|bumaqi:140|buyuanyima:2|74157:27|:23)
- 3 - B 21 AND2 0 3 0 4 |bumaqi:140|buyuanyima:2|74183:2|:13
- 2 - B 02 AND2 0 2 0 1 |bumaqi:140|buyuanyima:2|74183:2|:32
- 3 - B 05 AND2 0 4 0 1 |bumaqi:140|buyuanyima:2|74183:7|:32
- 4 - B 11 OR2 0 3 0 9 |bumaqi:140|buyuanyima:3|74157:26|Y2 (|bumaqi:140|buyuanyima:3|74157:26|:23)
- 2 - B 20 OR2 0 4 0 9 |bumaqi:140|buyuanyima:3|74157:26|Y3 (|bumaqi:140|buyuanyima:3|74157:26|:24)
- 1 - B 10 OR2 0 3 0 7 |bumaqi:140|buyuanyima:3|74157:26|Y4 (|bumaqi:140|buyuanyima:3|74157:26|:25)
- 5 - B 10 OR2 0 4 0 3 |bumaqi:140|buyuanyima:3|74157:27|Y2 (|bumaqi:140|buyuanyima:3|74157:27|:23)
- 4 - B 10 AND2 0 3 0 3 |bumaqi:140|buyuanyima:3|74183:2|:13
- 8 - B 10 AND2 0 2 0 4 |bumaqi:140|buyuanyima:3|74183:2|:32
- 6 - B 10 AND2 0 4 0 1 |bumaqi:140|buyuanyima:3|74183:7|:32
- 6 - B 01 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_0|:7
- 5 - B 11 AND2 0 4 0 3 |bumaqi:140|MULTI:75|one_bit_adder:U_0_0|:12
- 2 - B 11 OR2 s 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_1|~8~1
- 8 - B 11 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_1|:15
- 2 - B 12 OR2 0 2 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_2|:8
- 2 - B 01 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_2|:13
- 3 - B 12 OR2 0 4 0 3 |bumaqi:140|MULTI:75|one_bit_adder:U_0_2|:15
- 6 - B 12 OR2 0 3 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_3|:8
- 8 - B 12 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_4|:8
- 7 - B 01 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_0_4|:13
- 4 - B 12 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_0_4|:14
- 1 - B 01 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_0_4|:15
- 1 - B 11 OR2 0 4 0 3 |bumaqi:140|MULTI:75|one_bit_adder:U_1_0|:7
- 3 - B 11 OR2 0 4 0 3 |bumaqi:140|MULTI:75|one_bit_adder:U_1_0|:12
- 4 - B 04 OR2 s 0 3 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_1_1|~8~1
- 7 - B 12 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_1_1|:15
- 1 - B 12 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_1_2|:8
- 5 - B 12 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_1_2|:15
- 4 - B 08 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_1_3|:8
- 2 - B 08 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_1_3|:15
- 5 - B 04 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_2_0|:7
- 7 - B 04 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_2_0|:12
- 8 - B 08 OR2 0 4 0 4 |bumaqi:140|MULTI:75|one_bit_adder:U_2_1|:8
- 3 - B 08 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_2_1|:15
- 7 - B 08 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_2_2|:8
- 5 - B 08 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_2_2|:15
- 4 - B 07 AND2 0 2 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_3_0|:12
- 1 - B 07 OR2 0 4 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_3_1|:8
- 6 - B 08 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_3_1|:15
- 7 - B 07 OR2 0 3 0 2 |bumaqi:140|MULTI:75|one_bit_adder:U_4_0|:7
- 4 - B 01 OR2 s 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|~7~1
- 3 - B 01 OR2 s 0 3 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|~7~2
- 5 - B 05 OR2 s 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|~7~3
- 7 - B 05 OR2 s 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|~7~4
- 1 - B 08 OR2 s 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|~7~5
- 2 - B 07 OR2 0 4 0 1 |bumaqi:140|MULTI:75|one_bit_adder:U_5_0|:7
- 6 - B 17 AND2 0 2 0 1 |bumaqi:140|MULTI:75|:2088
- 7 - B 11 AND2 0 2 0 1 |bumaqi:140|MULTI:75|:2122
- 5 - B 01 AND2 0 2 0 4 |bumaqi:140|MULTI:75|:2156
- 4 - B 05 OR2 0 4 0 1 |bumaqi:140|MULTI:75|:2190
- 6 - B 11 AND2 0 2 0 1 |bumaqi:140|MULTI:75|:2325
- 8 - B 01 AND2 0 2 0 4 |bumaqi:140|MULTI:75|:2359
- 2 - B 10 OR2 0 4 0 4 |bumaqi:140|MULTI:75|:2875
- 7 - B 10 OR2 0 4 0 2 |bumaqi:140|MULTI:75|:2892
- 3 - B 10 OR2 0 4 0 1 |bumaqi:140|MULTI:75|:2909
- 8 - B 05 OR2 0 4 0 1 |bumaqi:140|MULTI:75|:3253
- 8 - B 20 OR2 0 4 0 1 |bumaqi:140|yuanbuyima:47|74157:24|Y2 (|bumaqi:140|yuanbuyima:47|74157:24|:23)
- 3 - B 04 OR2 0 3 0 1 |bumaqi:140|yuanbuyima:47|74157:24|Y3 (|bumaqi:140|yuanbuyima:47|74157:24|:24)
- 6 - B 04 OR2 0 4 0 1 |bumaqi:140|yuanbuyima:47|74157:24|Y4 (|bumaqi:140|yuanbuyima:47|74157:24|:25)
- 5 - B 07 OR2 0 4 0 1 |bumaqi:140|yuanbuyima:47|74157:25|Y1 (|bumaqi:140|yuanbuyima:47|74157:25|:22)
- 6 - B 07 OR2 0 3 0 1 |bumaqi:140|yuanbuyima:47|74157:25|Y2 (|bumaqi:140|yuanbuyima:47|74157:25|:23)
- 3 - B 07 OR2 0 4 0 1 |bumaqi:140|yuanbuyima:47|74157:25|Y3 (|bumaqi:140|yuanbuyima:47|74157:25|:24)
- 1 - B 04 OR2 0 3 0 3 |bumaqi:140|yuanbuyima:47|74183:2|2CN1 (|bumaqi:140|yuanbuyima:47|74183:2|:26)
- 2 - B 04 AND2 0 3 0 2 |bumaqi:140|yuanbuyima:47|74183:3|2CN1 (|bumaqi:140|yuanbuyima:47|74183:3|:26)
- 8 - B 07 OR2 0 3 0 2 |bumaqi:140|yuanbuyima:47|74183:4|:12
- 2 - B 05 OR2 0 2 0 7 |bumaqi:140|:46
- 2 - A 20 DFFE + 1 1 1 3 |cdu:28|cdu16:20|74163:1|f74163:sub|QA (|cdu:28|cdu16:20|74163:1|f74163:sub|:34)
- 6 - A 20 DFFE + 1 2 1 2 |cdu:28|cdu16:20|74163:1|f74163:sub|QB (|cdu:28|cdu16:20|74163:1|f74163:sub|:111)
- 8 - A 20 AND2 0 3 0 2 |cdu:28|cdu16:20|74163:1|f74163:sub|:119
- 7 - A 20 DFFE + 1 1 1 2 |cdu:28|cdu16:20|74163:1|f74163:sub|QC (|cdu:28|cdu16:20|74163:1|f74163:sub|:122)
- 1 - A 20 DFFE + 1 2 1 1 |cdu:28|cdu16:20|74163:1|f74163:sub|QD (|cdu:28|cdu16:20|74163:1|f74163:sub|:134)
- 2 - B 23 DFFE + 2 0 1 3 |cdu:28|cdu16:22|74163:1|f74163:sub|QA (|cdu:28|cdu16:22|74163:1|f74163:sub|:34)
- 1 - B 23 AND2 1 2 0 3 |cdu:28|cdu16:22|74163:1|f74163:sub|:106
- 6 - B 23 DFFE + 2 1 1 2 |cdu:28|cdu16:22|74163:1|f74163:sub|QB (|cdu:28|cdu16:22|74163:1|f74163:sub|:111)
- 4 - B 23 AND2 0 2 0 1 |cdu:28|cdu16:22|74163:1|f74163:sub|:117
- 3 - B 23 DFFE + 2 1 1 3 |cdu:28|cdu16:22|74163:1|f74163:sub|QC (|cdu:28|cdu16:22|74163:1|f74163:sub|:122)
- 8 - B 23 AND2 0 3 0 3 |cdu:28|cdu16:22|74163:1|f74163:sub|:128
- 5 - B 23 DFFE + 2 1 1 2 |cdu:28|cdu16:22|74163:1|f74163:sub|QD (|cdu:28|cdu16:22|74163:1|f74163:sub|:134)
- - 3 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_0
- - 1 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_1
- - 8 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_2
- - 6 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_3
- - 4 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_4
- - 5 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_5
- - 7 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_6
- - 2 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_7
- 1 - C 06 AND2 2 0 0 8 |LPM_RAM_IO:92|:91
- 5 - A 23 OR2 ! 3 0 0 4 |risel:121|2sel1:17|Y1 (|risel:121|2sel1:17|:101)
- 1 - A 23 OR2 3 1 0 2 |risel:121|4sel1:12|:6
- 2 - A 23 OR2 3 1 0 9 |risel:121|4sel1:12|:7
- 3 - A 23 OR2 3 1 0 4 |risel:121|4sel1:12|:8
- 4 - A 23 OR2 3 1 0 4 |risel:121|4sel1:12|:9
- 4 - A 13 AND2 2 1 0 8 |risel:121|R1LD (|risel:121|:8)
- 8 - A 13 AND2 2 1 0 8 |risel:121|R2LD (|risel:121|:9)
- 6 - A 13 AND2 2 1 0 8 |risel:121|R3LD (|risel:121|:10)
- 2 - A 13 AND2 2 1 0 8 |risel:121|R4LD (|risel:121|:11)
- 1 - A 14 OR2 ! 1 1 0 8 |risel:121|:19
- 2 - A 22 OR2 ! 1 1 0 6 |risel:121|:21
- 4 - A 14 OR2 ! 1 1 0 6 |risel:121|:22
- 7 - A 13 AND2 2 0 0 8 :24
- 5 - A 13 AND2 2 0 0 8 :26
- 2 - A 03 AND2 2 0 0 8 :85
- 3 - A 03 AND2 2 0 0 8 :130
- 7 - A 03 DFFE 1 2 0 5 |74161:78|f74161:sub|QA (|74161:78|f74161:sub|:9)
- 1 - A 19 AND2 0 2 0 1 |74161:78|f74161:sub|:84
- 3 - A 19 DFFE 1 3 0 4 |74161:78|f74161:sub|QB (|74161:78|f74161:sub|:87)
- 7 - A 19 AND2 0 3 0 1 |74161:78|f74161:sub|:94
- 2 - A 19 DFFE 1 3 0 3 |74161:78|f74161:sub|QC (|74161:78|f74161:sub|:99)
- 8 - A 19 AND2 0 4 0 4 |74161:78|f74161:sub|:104
- 6 - A 19 DFFE 1 3 0 2 |74161:78|f74161:sub|QD (|74161:78|f74161:sub|:110)
- 7 - A 11 DFFE 1 3 0 4 |74161:79|f74161:sub|QA (|74161:79|f74161:sub|:9)
- 6 - A 11 AND2 0 2 0 1 |74161:79|f74161:sub|:80
- 4 - A 11 AND2 0 3 0 1 |74161:79|f74161:sub|:84
- 3 - A 11 DFFE 1 3 0 3 |74161:79|f74161:sub|QB (|74161:79|f74161:sub|:87)
- 8 - A 11 AND2 0 4 0 1 |74161:79|f74161:sub|:94
- 2 - A 11 DFFE 1 3 0 2 |74161:79|f74161:sub|QC (|74161:79|f74161:sub|:99)
- 5 - A 11 DFFE 1 3 0 1 |74161:79|f74161:sub|QD (|74161:79|f74161:sub|:110)
- 2 - B 17 OR2 ! 2 2 0 2 |74181:11|:43
- 5 - B 20 OR2 ! 2 2 0 2 |74181:11|:44
- 2 - B 21 OR2 2 2 0 2 |74181:11|:45
- 4 - B 20 OR2 ! 2 2 0 2 |74181:11|:46
- 1 - B 20 OR2 ! 2 2 0 2 |74181:11|:47
- 7 - B 21 OR2 2 2 0 2 |74181:11|:48
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