📄 yunsuan11.rpt
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***** Logic for device 'yunsuan11' compiled without errors.
Device: EPF10K20TI144-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R
A E E E E E E E E
S G L R V P S S S S S S S S
L S G V W G N U I C C E 1 E E E E V E E E
L D B E N B D C B D B - N B D - - C - R 6 R R R R C R A R R A A
D D U L D U A C U A U B D U I B M B I B V 1 V V V V C V D V V D D
A N R S R I S E T N I S T S U I S N U U U N U E P E E E E I E R E E R R
R 7 2 2 I O 1 N 1 6 O 3 2 6 S O 0 T S L S T S D C D D D D O D 0 D D 3 7
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
N5 | 7 102 | ADR1
161LOAD | 8 101 | ADR5
S2 | 9 100 | ADR4
S0 | 10 99 | CN
RESERVED | 11 98 | N0
RESERVED | 12 97 | M
RESERVED | 13 96 | S3
WE | 14 95 | S1
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TI144-4 90 | RESERVED
RESERVED | 20 89 | RESERVED
N3 | 21 88 | BUS4
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
N2 | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
N1 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
D C B G T N R R V D R R L G L V V 1 C R G G R R V R T R R G A A R R V B
A L U N 2 4 E E C A E E D N D C C 6 L D N N E E C E 3 E E N D D E E C U
T R S D S S C T S S R D D C C 1 K D D S S C S S S D R R S S C S
0 N 7 I E E I 3 E E I I R I I C - I I E E I E E E I 2 6 E E I 5
O R R O R R O 1 N N L C N N R R O R R R O R R O
V V V V T T R D T T V V V V V V V
E E E E N U E E E E E E E
D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 5/22( 22%)
A3 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 2/2 1/2 6/22( 27%)
A4 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A7 6/ 8( 75%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A9 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
A13 6/ 8( 75%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A14 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 10/22( 45%)
A15 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
A16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 6/22( 27%)
A17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
A18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
A20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 8/22( 36%)
A21 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
A22 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 13/22( 59%)
A23 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
A24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
B1 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 11/22( 50%)
B2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 16/22( 72%)
B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B4 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
B7 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
B9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
B11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
B13 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 13/22( 59%)
B14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
B17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 16/22( 72%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
B21 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
B23 7/ 8( 87%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 17/22( 77%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 48/96 ( 50%)
Total logic cells used: 264/1152 ( 22%)
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 2.90/4 ( 72%)
Total fan-in: 768/4608 ( 16%)
Total input pins required: 30
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 264
Total flipflops required: 72
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 46/1152 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 7 8 1 0 6 1 8 1 8 0 8 6 7 7 8 8 1 8 8 8 8 5 8 130/8
B: 8 8 1 8 8 0 8 8 8 8 8 8 0 8 1 1 8 8 1 1 8 8 0 7 1 133/0
C: 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 16 8 8 16 9 1 14 9 16 9 16 8 8 14 8 8 16 16 2 9 16 16 8 12 9 264/8
Device-Specific Information: c:\maxplus2\multi\cpu\yunsuan11.rpt
yunsuan11
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT 0 0 0 8 ALU-BUS
55 - - - -- INPUT G 0 0 0 0 CLK-CDU
38 - - - 22 INPUT 0 0 0 8 CLRN
99 - - B -- INPUT 0 0 0 2 CN
37 - - - 23 INPUT 0 0 0 1 DAT0
136 - - - 20 INPUT 0 0 0 4 DAT1
132 - - - 16 INPUT 0 0 0 1 DAT2
46 - - - 17 INPUT 0 0 0 4 DAT3
137 - - - 20 INPUT 0 0 0 5 EN
144 - - A -- INPUT 0 0 0 1 LDAR
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