📄 kongzhiqi.rpt
字号:
8 - - - 03 OUTPUT 0 1 0 0 LDDR2
27 - - C -- OUTPUT 0 1 0 0 LDIR
79 - - - 24 OUTPUT 0 1 0 0 LDRI
62 - - C -- OUTPUT 0 0 0 0 M
83 - - - 13 OUTPUT 0 1 0 0 MUL
10 - - - 01 OUTPUT 0 1 0 0 PC_BUS
22 - - B -- OUTPUT 0 1 0 0 P1
39 - - - 11 OUTPUT 0 1 0 0 P2
81 - - - 22 OUTPUT 0 1 0 0 P3
49 - - - 16 OUTPUT 0 1 0 0 RD
28 - - C -- OUTPUT 0 1 0 0 RI_BUS
67 - - B -- OUTPUT 0 1 0 0 RI0
65 - - B -- OUTPUT 0 1 0 0 RI1
52 - - - 19 OUTPUT 0 1 0 0 RJ0
66 - - B -- OUTPUT 0 1 0 0 RJ1
16 - - A -- OUTPUT 0 1 0 0 SELRI
70 - - A -- OUTPUT 0 1 0 0 SW_BUS
36 - - - 07 OUTPUT 0 1 0 0 S0
19 - - A -- OUTPUT 0 1 0 0 S1
37 - - - 09 OUTPUT 0 1 0 0 S2
73 - - A -- OUTPUT 0 1 0 0 S3
18 - - A -- OUTPUT 0 1 0 0 WE
80 - - - 23 OUTPUT 0 1 0 0 161CLRN
58 - - C -- OUTPUT 0 1 0 0 161LOAD
30 - - C -- OUTPUT 0 1 0 0 161PC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\lx1111\kongzhiqi.rpt
kongzhiqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 07 OR2 1 2 0 1 |p1:60|:4
- 6 - B 07 OR2 1 2 0 1 |p1:60|:5
- 2 - B 05 OR2 1 2 0 1 |p1:60|:6
- 7 - B 07 OR2 1 2 0 1 |p1:60|:12
- 8 - A 05 DFFE + 0 4 1 22 |p1:60|7474:1|1Q (|p1:60|7474:1|:9)
- 4 - A 14 DFFE + 0 4 1 33 |p1:60|7474:1|2Q (|p1:60|7474:1|:10)
- 4 - B 07 DFFE + 0 4 0 1 |p1:60|7474:2|1Q (|p1:60|7474:2|:9)
- 4 - B 21 DFFE + 0 4 0 1 |p1:60|7474:2|2Q (|p1:60|7474:2|:10)
- 8 - A 11 DFFE + 0 4 0 1 |p1:60|7474:3|1Q (|p1:60|7474:3|:9)
- 8 - A 03 DFFE + ! 0 5 0 1 |p1:60|7474:3|2Q (|p1:60|7474:3|:10)
- 1 - B 19 OR2 1 2 0 1 |p2:61|:10
- 2 - B 24 OR2 1 2 0 1 |p2:61|:11
- 4 - B 19 DFFE + 0 4 0 1 |p2:61|7474:8|1Q (|p2:61|7474:8|:9)
- 8 - B 24 DFFE + 0 4 0 1 |p2:61|7474:8|2Q (|p2:61|7474:8|:10)
- 1 - B 13 OR2 1 2 0 1 |p3:62|:10
- 5 - B 20 OR2 1 2 0 1 |p3:62|:11
- 6 - B 13 DFFE + 0 4 0 1 |p3:62|7474:8|1Q (|p3:62|7474:8|:9)
- 6 - B 20 DFFE + 0 4 0 1 |p3:62|7474:8|2Q (|p3:62|7474:8|:10)
- 7 - A 11 DFFE + 0 3 0 1 |p3:62|7474:9|1Q (|p3:62|7474:9|:9)
- 5 - A 03 DFFE + 0 4 0 1 |p3:62|7474:9|2Q (|p3:62|7474:9|:10)
- 8 - A 22 OR2 ! 0 4 0 9 |ROM:71|:148
- 6 - A 12 OR2 ! 0 4 0 7 |ROM:71|:155
- 4 - A 12 OR2 ! 0 4 0 12 |ROM:71|:162
- 8 - A 08 OR2 s 0 3 0 10 |ROM:71|~169~1
- 1 - A 06 OR2 s 0 2 0 8 |ROM:71|~169~2
- 4 - A 11 OR2 ! 0 3 0 1 |ROM:71|:169
- 1 - A 02 OR2 ! 0 4 0 2 |ROM:71|:176
- 8 - A 12 OR2 s 0 3 0 7 |ROM:71|~183~1
- 4 - A 08 AND2 s ! 0 3 0 7 |ROM:71|~197~1
- 1 - A 21 AND2 0 2 0 1 |ROM:71|:204
- 1 - A 08 AND2 0 3 0 3 |ROM:71|:211
- 3 - A 05 OR2 ! 0 2 0 3 |ROM:71|:218
- 5 - A 22 OR2 ! 0 4 0 5 |ROM:71|:225
- 6 - A 22 OR2 ! 0 4 0 5 |ROM:71|:232
- 8 - A 14 OR2 ! 0 4 0 5 |ROM:71|:239
- 7 - A 13 OR2 ! 0 3 0 5 |ROM:71|:246
- 3 - A 14 OR2 s ! 0 2 0 3 |ROM:71|~253~1
- 1 - A 04 OR2 ! 0 3 0 3 |ROM:71|:253
- 2 - A 12 OR2 s ! 0 2 0 1 |ROM:71|~260~1
- 4 - A 04 OR2 ! 0 4 0 3 |ROM:71|:260
- 6 - A 13 OR2 ! 0 4 0 11 |ROM:71|:267
- 1 - A 13 OR2 s ! 0 2 0 7 |ROM:71|~274~1
- 5 - A 08 OR2 ! 0 4 0 9 |ROM:71|:274
- 5 - A 13 OR2 s ! 0 2 0 10 |ROM:71|~281~1
- 3 - A 13 OR2 ! 0 3 0 8 |ROM:71|:281
- 7 - A 22 AND2 0 4 0 7 |ROM:71|:288
- 7 - A 20 OR2 ! 0 4 0 9 |ROM:71|:295
- 6 - A 08 OR2 s ! 0 2 0 7 |ROM:71|~302~1
- 8 - A 13 AND2 0 4 0 8 |ROM:71|:302
- 5 - A 20 OR2 ! 0 4 0 9 |ROM:71|:309
- 1 - A 18 AND2 0 3 0 8 |ROM:71|:316
- 3 - A 08 AND2 s 0 2 0 10 |ROM:71|~323~1
- 2 - A 13 OR2 ! 0 4 0 8 |ROM:71|:323
- 7 - A 02 AND2 0 3 0 6 |ROM:71|:330
- 4 - A 22 OR2 ! 0 4 0 6 |ROM:71|:337
- 3 - A 06 AND2 0 3 0 6 |ROM:71|:344
- 3 - A 20 OR2 ! 0 4 0 6 |ROM:71|:351
- 3 - A 22 AND2 0 4 0 7 |ROM:71|:358
- 8 - A 20 OR2 s ! 0 2 0 9 |ROM:71|~365~1
- 1 - A 20 OR2 ! 0 4 0 4 |ROM:71|:365
- 1 - A 22 AND2 0 4 0 6 |ROM:71|:372
- 2 - A 20 OR2 ! 0 4 0 4 |ROM:71|:379
- 7 - A 12 AND2 0 4 0 7 |ROM:71|:386
- 4 - A 18 AND2 0 3 0 4 |ROM:71|:393
- 2 - A 08 OR2 s ! 0 2 0 12 |ROM:71|~400~1
- 6 - A 14 AND2 0 4 0 6 |ROM:71|:400
- 5 - A 18 AND2 s 0 3 0 4 |ROM:71|~407~1
- 1 - A 12 AND2 0 4 0 4 |ROM:71|:414
- 7 - A 15 OR2 s 0 2 0 3 |ROM:71|~652~1
- 2 - A 19 OR2 0 2 0 1 |ROM:71|:667
- 6 - A 19 OR2 0 4 0 1 |ROM:71|:681
- 2 - A 17 OR2 0 4 0 1 |ROM:71|:685
- 6 - A 09 OR2 s ! 0 3 0 1 |ROM:71|~766~1
- 5 - A 23 OR2 s 0 4 0 4 |ROM:71|~766~2
- 6 - A 23 OR2 s 0 2 0 1 |ROM:71|~766~3
- 8 - A 23 OR2 s 0 4 0 2 |ROM:71|~766~4
- 1 - A 23 OR2 s 0 3 0 1 |ROM:71|~766~5
- 6 - A 01 OR2 0 3 0 2 |ROM:71|:808
- 2 - A 23 OR2 s ! 0 3 0 4 |ROM:71|~876~1
- 3 - A 02 OR2 s ! 0 3 0 1 |ROM:71|~876~2
- 5 - A 02 AND2 0 4 0 1 |ROM:71|:876
- 6 - A 18 OR2 0 4 0 1 |ROM:71|:904
- 1 - A 19 OR2 0 4 0 1 |ROM:71|:918
- 8 - A 17 OR2 0 4 0 1 |ROM:71|:922
- 4 - A 02 OR2 0 4 0 1 |ROM:71|:999
- 2 - A 24 OR2 0 4 0 1 |ROM:71|:1086
- 3 - A 24 OR2 0 4 0 1 |ROM:71|:1111
- 6 - A 20 AND2 ! 0 2 0 3 |ROM:71|:1261
- 7 - A 17 OR2 0 4 0 1 |ROM:71|:1275
- 7 - A 23 AND2 s 0 2 0 1 |ROM:71|~1314~1
- 1 - A 17 OR2 0 4 0 1 |ROM:71|:1314
- 5 - A 14 AND2 s ! 0 3 0 9 |ROM:71|~1318~1
- 7 - A 21 AND2 s ! 0 2 0 1 |ROM:71|~1318~2
- 1 - A 16 OR2 0 4 0 1 |ROM:71|:1350
- 2 - A 18 OR2 0 4 0 2 |ROM:71|:1368
- 4 - A 01 AND2 s ! 0 2 0 3 |ROM:71|~1468~1
- 1 - A 14 OR2 s 0 3 0 5 |ROM:71|~1468~2
- 7 - A 18 OR2 s 0 3 0 1 |ROM:71|~1468~3
- 8 - A 04 OR2 s 0 2 0 2 |ROM:71|~1573~1
- 1 - A 05 OR2 ! 0 4 0 6 |ROM:71|:1573
- 7 - A 05 OR2 s ! 0 4 0 6 |ROM:71|~1824~1
- 2 - A 09 OR2 0 2 0 1 |ROM:71|:1999
- 1 - A 07 AND2 s 0 2 0 2 |ROM:71|~2124~1
- 7 - A 07 OR2 s 0 3 0 1 |ROM:71|~2124~2
- 4 - A 17 AND2 s ! 0 4 0 2 |ROM:71|~2329~1
- 8 - A 19 AND2 s ! 0 4 0 3 |ROM:71|~2329~2
- 7 - A 01 OR2 0 4 0 1 |ROM:71|:2337
- 5 - A 01 OR2 0 4 0 1 |ROM:71|:2341
- 8 - A 09 OR2 0 4 0 1 |ROM:71|:2355
- 4 - A 23 OR2 s 0 4 0 6 |ROM:71|~2407~1
- 3 - A 01 OR2 0 4 0 1 |ROM:71|:2455
- 6 - A 10 OR2 0 4 0 1 |ROM:71|:2469
- 1 - A 10 OR2 0 4 0 1 |ROM:71|:2473
- 4 - A 24 OR2 0 4 0 1 |ROM:71|:2485
- 8 - A 01 OR2 0 4 0 1 |ROM:71|:2566
- 1 - A 01 OR2 0 4 0 1 |ROM:71|:2580
- 7 - A 10 OR2 0 4 0 1 |ROM:71|:2584
- 8 - A 10 OR2 0 4 0 1 |ROM:71|:2601
- 7 - A 03 AND2 s ! 0 3 0 3 |ROM:71|~2611~1
- 2 - A 05 AND2 s ! 0 3 0 8 |ROM:71|~2641~1
- 6 - A 05 OR2 s 0 4 0 1 |ROM:71|~3573~1
- 3 - A 10 OR2 0 3 0 1 |ROM:71|:3636
- 5 - A 10 OR2 0 4 0 1 |ROM:71|:3640
- 7 - A 04 OR2 0 4 0 3 |ROM:71|:3654
- 2 - A 14 OR2 0 3 0 1 |ROM:71|:3660
- 7 - A 14 OR2 s 0 3 0 1 |ROM:71|~3685~1
- 4 - A 20 OR2 0 4 0 1 |ROM:71|:3723
- 5 - A 17 OR2 0 4 0 1 |ROM:71|:3727
- 6 - A 17 OR2 0 4 0 2 |ROM:71|:3741
- 4 - A 07 OR2 0 4 0 1 |ROM:71|:3745
- 2 - A 04 AND2 s 0 2 0 2 |ROM:71|~3786~1
- 5 - A 07 OR2 s 0 4 0 1 |ROM:71|~3786~2
- 5 - A 11 OR2 s 0 4 0 2 |ROM:71|~3790~1
- 3 - A 07 OR2 0 4 0 3 |ROM:71|:3790
- 2 - A 03 AND2 s 0 2 0 9 |ROM:71|~3813~1
- 5 - A 05 OR2 s 0 3 0 6 |ROM:71|~3813~2
- 1 - B 18 OR2 0 2 0 1 |ROM:71|:3826
- 2 - A 01 OR2 0 4 0 1 |ROM:71|:3856
- 3 - A 17 OR2 s ! 0 3 0 1 |ROM:71|~3858~1
- 6 - A 07 AND2 s 0 3 0 1 |ROM:71|~3876~1
- 8 - A 07 OR2 0 4 0 1 |ROM:71|:3882
- 5 - A 04 OR2 0 4 0 1 |ROM:71|:3903
- 6 - A 04 OR2 0 3 0 3 |ROM:71|:3912
- 8 - A 02 OR2 s 0 4 0 9 |ROM:71|~3930~1
- 3 - A 21 OR2 0 2 0 1 |ROM:71|:3955
- 4 - A 21 OR2 0 4 0 1 |ROM:71|:3979
- 2 - A 21 AND2 s 0 3 0 1 |ROM:71|~3981~1
- 3 - A 04 AND2 s 0 2 0 7 |ROM:71|~4005~1
- 6 - A 21 OR2 0 4 0 1 |ROM:71|:4005
- 8 - A 21 OR2 0 4 0 1 |ROM:71|:4012
- 5 - A 21 OR2 0 4 0 1 |ROM:71|:4021
- 1 - A 11 OR2 0 4 0 1 |ROM:71|:4029
- 2 - A 11 OR2 0 4 0 1 |ROM:71|:4035
- 6 - A 11 OR2 0 4 0 2 |ROM:71|:4044
- 3 - A 18 OR2 0 4 0 2 |ROM:71|:4057
- 2 - A 15 OR2 0 4 0 1 |ROM:71|:4069
- 3 - A 15 OR2 0 3 0 1 |ROM:71|:4081
- 4 - A 10 AND2 s ! 0 3 0 3 |ROM:71|~4129~1
- 4 - A 15 OR2 s 0 2 0 1 |ROM:71|~4129~2
- 1 - A 15 OR2 0 4 0 2 |ROM:71|:4129
- 4 - A 03 AND2 s ! 0 4 0 2 |ROM:71|~4164~1
- 4 - C 12 AND2 1 1 0 8 :35
- 2 - B 20 OR2 s 0 4 0 1 |74244:64|~10~1~3~2
- 3 - B 20 OR2 ! 0 3 1 19 |74244:64|~10~1~3
- 4 - B 20 OR2 s 0 4 0 1 |74244:64|~11~1~3~2
- 8 - B 20 OR2 ! 0 3 1 7 |74244:64|~11~1~3
- 3 - A 03 OR2 0 4 1 7 |74244:64|~31~1~3
- 3 - A 11 OR2 0 4 1 17 |74244:64|~36~1~3
- 8 - A 18 DFFE + 0 4 1 0 |74273:48|Q8 (|74273:48|:12)
- 2 - A 16 DFFE + 0 3 1 0 |74273:48|Q7 (|74273:48|:13)
- 5 - A 12 DFFE + 0 4 1 0 |74273:48|Q6 (|74273:48|:14)
- 1 - A 24 DFFE + 0 4 1 0 |74273:48|Q5 (|74273:48|:15)
- 2 - A 02 DFFE + 0 4 1 0 |74273:48|Q4 (|74273:48|:16)
- 6 - A 02 DFFE + 0 4 1 0 |74273:48|Q3 (|74273:48|:17)
- 7 - C 17 DFFE + 0 4 1 0 |74273:48|Q2 (|74273:48|:18)
- 3 - A 23 DFFE + 0 4 1 0 |74273:48|Q1 (|74273:48|:19)
- 4 - A 09 DFFE + 0 4 1 0 |74273:49|Q8 (|74273:49|:12)
- 3 - A 09 DFFE + 0 3 1 0 |74273:49|Q7 (|74273:49|:13)
- 2 - A 07 DFFE + 0 4 1 0 |74273:49|Q6 (|74273:49|:14)
- 7 - A 09 DFFE + 0 4 1 0 |74273:49|Q5 (|74273:49|:15)
- 5 - A 09 DFFE + 0 1 1 0 |74273:49|Q4 (|74273:49|:16)
- 1 - A 09 DFFE + 0 3 1 0 |74273:49|Q3 (|74273:49|:17)
- 4 - A 05 DFFE + 0 2 1 0 |74273:49|Q1 (|74273:49|:19)
- 1 - B 20 DFFE 1 1 1 1 |74273:50|Q8 (|74273:50|:12)
- 3 - B 13 DFFE 1 1 1 1 |74273:50|Q7 (|74273:50|:13)
- 1 - B 24 DFFE 1 1 1 1 |74273:50|Q6 (|74273:50|:14)
- 5 - B 19 DFFE 1 1 1 1 |74273:50|Q5 (|74273:50|:15)
- 8 - B 07 DFFE 1 1 0 1 |74273:50|Q4 (|74273:50|:16)
- 1 - B 05 DFFE 1 1 0 1 |74273:50|Q3 (|74273:50|:17)
- 5 - B 07 DFFE 1 1 0 1 |74273:50|Q2 (|74273:50|:18)
- 1 - B 07 DFFE 1 1 0 1 |74273:50|Q1 (|74273:50|:19)
- 2 - A 22 DFFE + 0 4 1 8 |74273:51|Q8 (|74273:51|:12)
- 3 - A 12 DFFE + 0 4 1 6 |74273:51|Q7 (|74273:51|:13)
- 2 - B 07 DFFE + 0 1 1 4 |74273:51|Q6 (|74273:51|:14)
- 1 - C 12 DFFE + 0 1 1 1 |74273:51|Q5 (|74273:51|:15)
- 6 - A 03 DFFE + 0 4 1 0 |74273:51|Q4 (|74273:51|:16)
- 1 - A 03 DFFE + 0 4 1 0 |74273:51|Q3 (|74273:51|:17)
- 2 - A 10 DFFE + 0 4 1 0 |74273:51|Q2 (|74273:51|:18)
- 5 - A 24 DFFE + 0 4 1 0 |74273:51|Q1 (|74273:51|:19)
- 4 - A 13 DFFE + 0 4 1 0 |74273:72|Q1 (|74273:72|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\lx1111\kongzhiqi.rpt
kongzhiqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 64/ 96( 66%) 37/ 48( 77%) 34/ 48( 70%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 16/ 96( 16%) 4/ 48( 8%) 9/ 48( 18%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 1/ 96( 1%) 4/ 48( 8%) 6/ 48( 12%) 1/16( 6%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\lx1111\kongzhiqi.rpt
kongzhiqi
** CLOCK SIGNALS **
Type Fan-out Name
⌨️ 快捷键说明
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