📄 alu11.rpt
字号:
alu11
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A8 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A9 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
B2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B3 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 13/22( 59%)
B4 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
B5 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 13/22( 59%)
B6 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 8/22( 36%)
B7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B8 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 7/22( 31%)
B9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
B10 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B11 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 13/22( 59%)
B12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B17 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B20 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
B21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
C1 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 6/22( 27%)
C2 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
C6 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 2/2 0/2 9/22( 40%)
C9 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
C12 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
C13 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 9/22( 40%)
C14 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
C15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 8/22( 36%)
C16 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 11/22( 50%)
C18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 12/22( 54%)
C19 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
C20 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 17/22( 77%)
C21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 12/22( 54%)
C22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
C23 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
B25 7/8 ( 87%) 3/8 ( 37%) 4/8 ( 50%) 1/2 2/2 16/22( 72%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 48/53 ( 90%)
Total logic cells used: 224/576 ( 38%)
Total embedded cells used: 7/24 ( 29%)
Total EABs used: 1/3 ( 33%)
Average fan-in: 2.90/4 ( 72%)
Total fan-in: 651/2304 ( 28%)
Total input pins required: 31
Total input I/O cell registers required: 0
Total output pins required: 23
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 224
Total flipflops required: 69
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 46/ 576 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10/0
B: 8 8 7 6 6 7 8 8 8 6 6 8 7 1 0 1 0 7 0 1 7 8 0 0 0 111/7
C: 8 5 0 0 0 8 0 0 2 0 0 2 0 8 2 8 5 8 8 8 8 8 8 6 1 103/0
Total: 16 13 7 6 6 15 8 10 18 6 6 10 7 9 2 9 5 15 8 9 15 16 8 6 1 224/7
Device-Specific Information: d:\computer\alu\alu11.rpt
alu11
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 8 ALU-BUS
43 - - - -- INPUT G 0 0 0 0 CDUCLK
29 - - C -- INPUT 0 0 0 7 CLR
80 - - - 23 INPUT 0 0 0 2 CN
17 - - A -- INPUT 0 0 0 1 DR0
73 - - A -- INPUT 0 0 0 1 DR1
70 - - A -- INPUT 0 0 0 1 DR2
69 - - A -- INPUT 0 0 0 1 DR3
51 - - - 18 INPUT 0 0 0 6 EN
16 - - A -- INPUT 0 0 0 1 LDAR
81 - - - 22 INPUT 0 0 0 1 LDRA
36 - - - 07 INPUT 0 0 0 1 LDRB
30 - - C -- INPUT 0 0 0 4 LDRi
23 - - B -- INPUT 0 0 0 7 M
66 - - B -- INPUT 0 0 0 7 MUL
47 - - - 14 INPUT 0 0 0 8 PC-BUS
84 - - - -- INPUT 0 0 0 8 RD
42 - - - -- INPUT 0 0 0 19 Ri-BUS
72 - - A -- INPUT 0 0 0 2 SELRi
50 - - - 17 INPUT 0 0 0 1 SIGNAL
53 - - - 20 INPUT 0 0 0 8 SW-BUS
65 - - B -- INPUT 0 0 0 7 S0
24 - - B -- INPUT 0 0 0 7 S1
64 - - B -- INPUT 0 0 0 7 S2
67 - - B -- INPUT 0 0 0 7 S3
1 - - - -- INPUT G 0 0 0 6 T2
71 - - A -- INPUT 0 0 0 2 T3
78 - - - 24 INPUT 0 0 0 1 WE
2 - - - -- INPUT G 0 0 0 0 161CLRN
28 - - C -- INPUT 0 0 0 8 161LOAD
19 - - A -- INPUT 0 0 0 1 161PC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\computer\alu\alu11.rpt
alu11
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- OUTPUT 0 1 0 0 ADR1
21 - - B -- OUTPUT 0 1 0 0 ADR2
9 - - - 02 OUTPUT 0 1 0 0 ADR3
25 - - B -- OUTPUT 0 1 0 0 ADR4
37 - - - 09 OUTPUT 0 1 0 0 ADR5
11 - - - 01 OUTPUT 0 1 0 0 ADR6
18 - - A -- OUTPUT 0 1 0 0 ADR7
38 - - - 10 OUTPUT 0 1 0 0 ADR8
10 - - - 01 OUTPUT 0 1 0 0 BUS1
54 - - - 21 OUTPUT 0 1 0 0 BUS2
52 - - - 19 OUTPUT 0 1 0 0 BUS3
39 - - - 11 OUTPUT 0 1 0 0 BUS4
5 - - - 05 OUTPUT 0 1 0 0 BUS5
79 - - - 24 OUTPUT 0 1 0 0 BUS6
8 - - - 03 OUTPUT 0 1 0 0 BUS7
48 - - - 15 OUTPUT 0 1 0 0 BUS8
83 - - - 13 OUTPUT 0 1 0 0 Q1
58 - - C -- OUTPUT 0 1 0 0 Q2
27 - - C -- OUTPUT 0 1 0 0 Q3
59 - - C -- OUTPUT 0 1 0 0 Q4
62 - - C -- OUTPUT 0 1 0 0 Q5
60 - - C -- OUTPUT 0 1 0 0 Q6
61 - - C -- OUTPUT 0 1 0 0 Q7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\alu11.rpt
alu11
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 16 DFFE + 1 2 1 2 |cdu:97|cdu16:1|74163:1|f74163:sub|QA (|cdu:97|cdu16:1|74163:1|f74163:sub|:34)
- 4 - C 16 AND2 0 3 0 2 |cdu:97|cdu16:1|74163:1|f74163:sub|:108
- 3 - C 16 DFFE + 1 1 1 2 |cdu:97|cdu16:1|74163:1|f74163:sub|QB (|cdu:97|cdu16:1|74163:1|f74163:sub|:111)
- 2 - C 16 DFFE + 1 2 1 1 |cdu:97|cdu16:1|74163:1|f74163:sub|QC (|cdu:97|cdu16:1|74163:1|f74163:sub|:122)
- 5 - C 13 DFFE + 2 0 1 4 |cdu:97|cdu16:2|74163:1|f74163:sub|QA (|cdu:97|cdu16:2|74163:1|f74163:sub|:34)
- 8 - C 13 AND2 1 2 0 1 |cdu:97|cdu16:2|74163:1|f74163:sub|:106
- 7 - C 13 DFFE + 2 1 1 3 |cdu:97|cdu16:2|74163:1|f74163:sub|QB (|cdu:97|cdu16:2|74163:1|f74163:sub|:111)
- 4 - C 13 AND2 1 3 0 3 |cdu:97|cdu16:2|74163:1|f74163:sub|:117
- 1 - C 13 DFFE + 2 1 1 2 |cdu:97|cdu16:2|74163:1|f74163:sub|QC (|cdu:97|cdu16:2|74163:1|f74163:sub|:122)
- 5 - C 16 DFFE + 2 1 1 3 |cdu:97|cdu16:2|74163:1|f74163:sub|QD (|cdu:97|cdu16:2|74163:1|f74163:sub|:134)
- - 8 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_1
- - 2 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_2
- - 6 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_3
- - 4 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_4
- - 5 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_5
- - 1 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_6
- - 3 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:35|altram:sram|segment0_7
- 1 - B 13 AND2 2 0 0 7 |LPM_RAM_IO:35|:90
- 6 - B 21 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_0_0|:7
- 8 - B 21 AND2 0 4 0 3 |MULTI:42|one_bit_adder:U_0_0|:12
- 1 - B 20 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_1|:8
- 3 - B 12 AND2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_1|:12
- 4 - B 12 OR2 0 3 0 1 |MULTI:42|one_bit_adder:U_0_1|:15
- 7 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_2|:8
- 1 - B 08 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_2|:13
- 6 - B 12 OR2 0 3 0 4 |MULTI:42|one_bit_adder:U_0_2|:15
- 2 - B 08 OR2 0 4 0 4 |MULTI:42|one_bit_adder:U_0_3|:13
- 1 - B 12 AND2 0 2 0 1 |MULTI:42|one_bit_adder:U_0_3|:14
- 7 - B 01 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_4|:8
- 2 - B 01 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_4|:13
- 6 - B 01 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_0_4|:15
- 7 - B 17 OR2 0 3 0 1 |MULTI:42|one_bit_adder:U_1_0|:7
- 4 - B 17 AND2 0 3 0 2 |MULTI:42|one_bit_adder:U_1_0|:12
- 1 - B 02 OR2 0 4 0 3 |MULTI:42|one_bit_adder:U_1_1|:8
- 4 - B 02 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_1|:15
- 5 - B 12 OR2 0 4 0 3 |MULTI:42|one_bit_adder:U_1_2|:8
- 2 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_2|:15
- 3 - B 01 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_3|:8
- 8 - B 01 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_1_3|:15
- 5 - B 02 OR2 0 3 0 1 |MULTI:42|one_bit_adder:U_2_0|:7
- 3 - B 02 AND2 0 3 0 1 |MULTI:42|one_bit_adder:U_2_0|:12
- 7 - B 02 OR2 s 0 4 0 2 |MULTI:42|one_bit_adder:U_2_1|~8~1
- 8 - B 02 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_2_1|:15
- 6 - B 02 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_2_2|:8
- 2 - B 02 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_2_2|:15
- 1 - B 09 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_3_0|:7
- 2 - B 09 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_3_0|:12
- 5 - B 09 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_3_1|:8
- 4 - B 09 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_3_1|:15
- 6 - B 09 OR2 0 3 0 1 |MULTI:42|one_bit_adder:U_4_0|:7
- 7 - B 09 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~1
- 1 - B 01 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -