temp.rpt
来自「vhd语言」· RPT 代码 · 共 879 行 · 第 1/3 页
RPT
879 行
-- Node name is '|74374:13|:14'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = DFFE( BUS2, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:15'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( BUS3, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:16'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = DFFE( BUS4, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:17'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = DFFE( BUS5, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:18'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = DFFE( BUS6, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:19'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = DFFE( BUS7, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|:20'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = DFFE( BUS8, _LC2_B24, VCC, VCC, VCC);
-- Node name is '|74374:13|~40~1~2'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( VCC);
-- Node name is '|74374:13|~40~1~3~2'
-- Equation name is '_LC4_B24', type is buried
-- synthesized logic cell
_LC4_B24 = LCELL( _EQ017);
_EQ017 = _LC6_B24 & RI-BUS;
-- Node name is '|74374:13|~40~1~3~3'
-- Equation name is '_LC7_B16', type is buried
-- synthesized logic cell
_LC7_B16 = LCELL( _EQ018);
_EQ018 = BUS & _LC8_B16
# BUS & _LC5_B24
# _LC3_B19 & _LC8_B16
# _LC3_B19 & _LC5_B24;
-- Node name is '|74374:13|~40~1~3'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ019);
_EQ019 = _LC3_B18 & _LC4_B24 & _LC7_B16
# _LC3_B24 & _LC4_B24 & _LC7_B16;
-- Node name is '|74374:13|~41~1~3~2'
-- Equation name is '_LC3_B16', type is buried
-- synthesized logic cell
_LC3_B16 = LCELL( _EQ020);
_EQ020 = BUS & _LC4_B16
# BUS & _LC5_B24
# _LC2_B19 & _LC4_B16
# _LC2_B19 & _LC5_B24;
-- Node name is '|74374:13|~41~1~3'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ021);
_EQ021 = _LC1_B18 & _LC3_B16 & _LC4_B24
# _LC3_B16 & _LC3_B24 & _LC4_B24;
-- Node name is '|74374:13|~42~1~3~2'
-- Equation name is '_LC1_B22', type is buried
-- synthesized logic cell
_LC1_B22 = LCELL( _EQ022);
_EQ022 = BUS & _LC2_B22
# BUS & _LC5_B24
# _LC2_B16 & _LC2_B22
# _LC2_B16 & _LC5_B24;
-- Node name is '|74374:13|~42~1~3'
-- Equation name is '_LC6_B22', type is buried
_LC6_B22 = LCELL( _EQ023);
_EQ023 = _LC1_B22 & _LC4_B24 & _LC5_B22
# _LC1_B22 & _LC3_B24 & _LC4_B24;
-- Node name is '|74374:13|~43~1~3~2'
-- Equation name is '_LC2_B13', type is buried
-- synthesized logic cell
_LC2_B13 = LCELL( _EQ024);
_EQ024 = BUS & _LC3_B13
# BUS & _LC5_B24
# _LC1_B19 & _LC3_B13
# _LC1_B19 & _LC5_B24;
-- Node name is '|74374:13|~43~1~3'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ025);
_EQ025 = _LC2_B13 & _LC4_B24 & _LC7_B13
# _LC2_B13 & _LC3_B24 & _LC4_B24;
-- Node name is '|74374:13|~44~1~3~2'
-- Equation name is '_LC4_B13', type is buried
-- synthesized logic cell
_LC4_B13 = LCELL( _EQ026);
_EQ026 = BUS & _LC5_B13
# BUS & _LC5_B24
# _LC5_B13 & _LC6_B19
# _LC5_B24 & _LC6_B19;
-- Node name is '|74374:13|~44~1~3'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ027);
_EQ027 = _LC4_B13 & _LC4_B24 & _LC8_B13
# _LC3_B24 & _LC4_B13 & _LC4_B24;
-- Node name is '|74374:13|~45~1~3~2'
-- Equation name is '_LC3_B22', type is buried
-- synthesized logic cell
_LC3_B22 = LCELL( _EQ028);
_EQ028 = BUS & _LC4_B22
# BUS & _LC5_B24
# _LC4_B22 & _LC8_B19
# _LC5_B24 & _LC8_B19;
-- Node name is '|74374:13|~45~1~3'
-- Equation name is '_LC8_B22', type is buried
_LC8_B22 = LCELL( _EQ029);
_EQ029 = _LC3_B22 & _LC4_B24 & _LC7_B22
# _LC3_B22 & _LC3_B24 & _LC4_B24;
-- Node name is '|74374:13|~46~1~3~2'
-- Equation name is '_LC1_B21', type is buried
-- synthesized logic cell
_LC1_B21 = LCELL( _EQ030);
_EQ030 = BUS & _LC2_B21
# BUS & _LC5_B24
# _LC2_B21 & _LC5_B21
# _LC5_B21 & _LC5_B24;
-- Node name is '|74374:13|~46~1~3'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ031);
_EQ031 = _LC1_B21 & _LC4_B18 & _LC4_B24
# _LC1_B21 & _LC3_B24 & _LC4_B24;
-- Node name is '|74374:13|~47~1~3~2'
-- Equation name is '_LC6_B21', type is buried
-- synthesized logic cell
_LC6_B21 = LCELL( _EQ032);
_EQ032 = BUS & _LC7_B21
# BUS & _LC5_B24
# _LC7_B21 & _LC8_B21
# _LC5_B24 & _LC8_B21;
-- Node name is '|74374:13|~47~1~3'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ033);
_EQ033 = _LC2_B18 & _LC4_B24 & _LC6_B21
# _LC3_B24 & _LC4_B24 & _LC6_B21;
-- Node name is '|74374:14|:13'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = DFFE( BUS1, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:14'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = DFFE( BUS2, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:15'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = DFFE( BUS3, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:16'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = DFFE( BUS4, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:17'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = DFFE( BUS5, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:18'
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = DFFE( BUS6, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:19'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = DFFE( BUS7, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|74374:14|:20'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = DFFE( BUS8, _LC1_B24, VCC, VCC, VCC);
-- Node name is ':10'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ034);
_EQ034 = !_LC3_B24 & LDRI;
-- Node name is ':11'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ035);
_EQ035 = !_LC3_B24 & LDRI & !RI-BUS;
Project Information d:\computer\alu\temp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,254K
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