temp.rpt
来自「vhd语言」· RPT 代码 · 共 879 行 · 第 1/3 页
RPT
879 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\temp.rpt
temp
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 19 DFFE + 1 2 0 3 |cdu:40|cdu16:1|74163:1|f74163:sub|QA (|cdu:40|cdu16:1|74163:1|f74163:sub|:34)
- 8 - B 19 DFFE + 1 2 0 2 |cdu:40|cdu16:1|74163:1|f74163:sub|QB (|cdu:40|cdu16:1|74163:1|f74163:sub|:111)
- 4 - B 19 AND2 0 4 0 2 |cdu:40|cdu16:1|74163:1|f74163:sub|:119
- 5 - B 21 DFFE + 1 1 0 2 |cdu:40|cdu16:1|74163:1|f74163:sub|QC (|cdu:40|cdu16:1|74163:1|f74163:sub|:122)
- 8 - B 21 DFFE + 1 2 0 1 |cdu:40|cdu16:1|74163:1|f74163:sub|QD (|cdu:40|cdu16:1|74163:1|f74163:sub|:134)
- 3 - B 19 DFFE + 2 0 0 4 |cdu:40|cdu16:2|74163:1|f74163:sub|QA (|cdu:40|cdu16:2|74163:1|f74163:sub|:34)
- 6 - B 16 AND2 1 2 0 1 |cdu:40|cdu16:2|74163:1|f74163:sub|:106
- 2 - B 19 DFFE + 2 1 0 3 |cdu:40|cdu16:2|74163:1|f74163:sub|QB (|cdu:40|cdu16:2|74163:1|f74163:sub|:111)
- 5 - B 19 AND2 1 3 0 4 |cdu:40|cdu16:2|74163:1|f74163:sub|:117
- 2 - B 16 DFFE + 2 1 0 2 |cdu:40|cdu16:2|74163:1|f74163:sub|QC (|cdu:40|cdu16:2|74163:1|f74163:sub|:122)
- 7 - B 19 AND2 0 2 0 1 |cdu:40|cdu16:2|74163:1|f74163:sub|:128
- 1 - B 19 DFFE + 2 1 0 4 |cdu:40|cdu16:2|74163:1|f74163:sub|QD (|cdu:40|cdu16:2|74163:1|f74163:sub|:134)
- 7 - B 24 OR2 ! 3 0 0 2 |2sel1:5|Y1 (|2sel1:5|:101)
- 6 - B 24 OR2 3 0 0 3 |2sel1:5|Y2 (|2sel1:5|:102)
- 3 - B 24 AND2 ! 0 2 0 10 |4sel1:1|Y2N (|4sel1:1|:8)
- 5 - B 24 OR2 0 2 0 8 |4sel1:1|Y3N (|4sel1:1|:9)
- 1 - B 24 AND2 1 1 0 8 :10
- 2 - B 24 AND2 2 1 0 8 :11
- 8 - B 16 DFFE 0 2 0 1 |74374:13|:13
- 4 - B 16 DFFE 0 2 0 1 |74374:13|:14
- 2 - B 22 DFFE 0 2 0 1 |74374:13|:15
- 3 - B 13 DFFE 0 2 0 1 |74374:13|:16
- 5 - B 13 DFFE 0 2 0 1 |74374:13|:17
- 4 - B 22 DFFE 0 2 0 1 |74374:13|:18
- 2 - B 21 DFFE 0 2 0 1 |74374:13|:19
- 7 - B 21 DFFE 0 2 0 1 |74374:13|:20
- 1 - C 12 AND2 0 0 0 0 |74374:13|~40~1~2
- 4 - B 24 AND2 s 1 1 0 8 |74374:13|~40~1~3~2
- 7 - B 16 OR2 s 1 3 0 1 |74374:13|~40~1~3~3
- 1 - B 16 OR2 0 4 1 0 |74374:13|~40~1~3
- 3 - B 16 OR2 s 1 3 0 1 |74374:13|~41~1~3~2
- 5 - B 16 OR2 0 4 1 0 |74374:13|~41~1~3
- 1 - B 22 OR2 s 1 3 0 1 |74374:13|~42~1~3~2
- 6 - B 22 OR2 0 4 1 0 |74374:13|~42~1~3
- 2 - B 13 OR2 s 1 3 0 1 |74374:13|~43~1~3~2
- 1 - B 13 OR2 0 4 1 0 |74374:13|~43~1~3
- 4 - B 13 OR2 s 1 3 0 1 |74374:13|~44~1~3~2
- 6 - B 13 OR2 0 4 1 0 |74374:13|~44~1~3
- 3 - B 22 OR2 s 1 3 0 1 |74374:13|~45~1~3~2
- 8 - B 22 OR2 0 4 1 0 |74374:13|~45~1~3
- 1 - B 21 OR2 s 1 3 0 1 |74374:13|~46~1~3~2
- 4 - B 21 OR2 0 4 1 0 |74374:13|~46~1~3
- 6 - B 21 OR2 s 1 3 0 1 |74374:13|~47~1~3~2
- 3 - B 21 OR2 0 4 1 0 |74374:13|~47~1~3
- 3 - B 18 DFFE 0 2 0 1 |74374:14|:13
- 1 - B 18 DFFE 0 2 0 1 |74374:14|:14
- 5 - B 22 DFFE 0 2 0 1 |74374:14|:15
- 7 - B 13 DFFE 0 2 0 1 |74374:14|:16
- 8 - B 13 DFFE 0 2 0 1 |74374:14|:17
- 7 - B 22 DFFE 0 2 0 1 |74374:14|:18
- 4 - B 18 DFFE 0 2 0 1 |74374:14|:19
- 2 - B 18 DFFE 0 2 0 1 |74374:14|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\temp.rpt
temp
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 21/ 96( 21%) 0/ 48( 0%) 17/ 48( 35%) 1/16( 6%) 0/16( 0%) 8/16( 50%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\temp.rpt
temp
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
LCELL 8 :10
LCELL 8 :11
Device-Specific Information: d:\computer\alu\temp.rpt
temp
** EQUATIONS **
BUS : INPUT;
CLK : INPUT;
CLRN : INPUT;
DR1 : INPUT;
DR2 : INPUT;
DR3 : INPUT;
DR4 : INPUT;
EN : INPUT;
LDRI : INPUT;
RI-BUS : INPUT;
SELRI : INPUT;
-- Node name is 'BUS1'
-- Equation name is 'BUS1', type is bidir
BUS1 = TRI(_LC1_B16, _LC1_C12);
-- Node name is 'BUS2'
-- Equation name is 'BUS2', type is bidir
BUS2 = TRI(_LC5_B16, _LC1_C12);
-- Node name is 'BUS3'
-- Equation name is 'BUS3', type is bidir
BUS3 = TRI(_LC6_B22, _LC1_C12);
-- Node name is 'BUS4'
-- Equation name is 'BUS4', type is bidir
BUS4 = TRI(_LC1_B13, _LC1_C12);
-- Node name is 'BUS5'
-- Equation name is 'BUS5', type is bidir
BUS5 = TRI(_LC6_B13, _LC1_C12);
-- Node name is 'BUS6'
-- Equation name is 'BUS6', type is bidir
BUS6 = TRI(_LC8_B22, _LC1_C12);
-- Node name is 'BUS7'
-- Equation name is 'BUS7', type is bidir
BUS7 = TRI(_LC4_B21, _LC1_C12);
-- Node name is 'BUS8'
-- Equation name is 'BUS8', type is bidir
BUS8 = TRI(_LC3_B21, _LC1_C12);
-- Node name is '|cdu:40|cdu16:1|74163:1|f74163:sub|:34' = '|cdu:40|cdu16:1|74163:1|f74163:sub|QA'
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = CLRN & !_LC1_B19 & _LC6_B19
# CLRN & !_LC5_B19 & _LC6_B19
# CLRN & _LC1_B19 & _LC5_B19 & !_LC6_B19;
-- Node name is '|cdu:40|cdu16:1|74163:1|f74163:sub|:111' = '|cdu:40|cdu16:1|74163:1|f74163:sub|QB'
-- Equation name is '_LC8_B19', type is buried
_LC8_B19 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = CLRN & !_LC7_B19 & _LC8_B19
# CLRN & !_LC6_B19 & _LC8_B19
# CLRN & _LC6_B19 & _LC7_B19 & !_LC8_B19;
-- Node name is '|cdu:40|cdu16:1|74163:1|f74163:sub|:122' = '|cdu:40|cdu16:1|74163:1|f74163:sub|QC'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = CLRN & !_LC4_B19 & _LC5_B21
# CLRN & _LC4_B19 & !_LC5_B21;
-- Node name is '|cdu:40|cdu16:1|74163:1|f74163:sub|:134' = '|cdu:40|cdu16:1|74163:1|f74163:sub|QD'
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = CLRN & !_LC5_B21 & _LC8_B21
# CLRN & !_LC4_B19 & _LC8_B21
# CLRN & _LC4_B19 & _LC5_B21 & !_LC8_B21;
-- Node name is '|cdu:40|cdu16:1|74163:1|f74163:sub|:119'
-- Equation name is '_LC4_B19', type is buried
_LC4_B19 = LCELL( _EQ005);
_EQ005 = _LC1_B19 & _LC5_B19 & _LC6_B19 & _LC8_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:34' = '|cdu:40|cdu16:2|74163:1|f74163:sub|QA'
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = CLRN & !EN & _LC3_B19
# CLRN & EN & !_LC3_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:111' = '|cdu:40|cdu16:2|74163:1|f74163:sub|QB'
-- Equation name is '_LC2_B19', type is buried
_LC2_B19 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = CLRN & _LC2_B19 & !_LC3_B19
# CLRN & !EN & _LC2_B19
# CLRN & EN & !_LC2_B19 & _LC3_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:122' = '|cdu:40|cdu16:2|74163:1|f74163:sub|QC'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = CLRN & _LC2_B16 & !_LC6_B16
# CLRN & !EN & _LC2_B16
# CLRN & EN & !_LC2_B16 & _LC6_B16;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:134' = '|cdu:40|cdu16:2|74163:1|f74163:sub|QD'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = CLRN & _LC1_B19 & !_LC5_B19
# CLRN & !EN & _LC1_B19
# CLRN & EN & !_LC1_B19 & _LC5_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:106'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = LCELL( _EQ010);
_EQ010 = EN & _LC2_B19 & _LC3_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:117'
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = LCELL( _EQ011);
_EQ011 = EN & _LC2_B16 & _LC2_B19 & _LC3_B19;
-- Node name is '|cdu:40|cdu16:2|74163:1|f74163:sub|:128'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ012);
_EQ012 = _LC1_B19 & _LC5_B19;
-- Node name is '|2sel1:5|:101' = '|2sel1:5|Y1'
-- Equation name is '_LC7_B24', type is buried
!_LC7_B24 = _LC7_B24~NOT;
_LC7_B24~NOT = LCELL( _EQ013);
_EQ013 = !DR3 & !DR4
# !DR3 & SELRI
# !DR4 & !SELRI;
-- Node name is '|2sel1:5|:102' = '|2sel1:5|Y2'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ014);
_EQ014 = DR2 & !SELRI
# DR1 & SELRI;
-- Node name is '|4sel1:1|:8' = '|4sel1:1|Y2N'
-- Equation name is '_LC3_B24', type is buried
!_LC3_B24 = _LC3_B24~NOT;
_LC3_B24~NOT = LCELL( _EQ015);
_EQ015 = _LC6_B24 & !_LC7_B24;
-- Node name is '|4sel1:1|:9' = '|4sel1:1|Y3N'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ016);
_EQ016 = !_LC7_B24
# !_LC6_B24;
-- Node name is '|74374:13|:13'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE( BUS1, _LC2_B24, VCC, VCC, VCC);
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