alu22.rpt

来自「vhd语言」· RPT 代码 · 共 1,381 行 · 第 1/5 页

RPT
1,381
字号
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                         d:\computer\alu\alu22.rpt
alu22

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      11/ 96( 11%)     0/ 48(  0%)    13/ 48( 27%)    8/16( 50%)      0/16(  0%)     0/16(  0%)
B:      48/ 96( 50%)    28/ 48( 58%)    22/ 48( 45%)    1/16(  6%)      3/16( 18%)     5/16( 31%)
C:       1/ 96(  1%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      5/24( 20%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
14:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
15:      5/24( 20%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      3/24( 12%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
18:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      5/24( 20%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         d:\computer\alu\alu22.rpt
alu22

** CLOCK SIGNALS **

Type     Fan-out       Name
LCELL        8         |risel:128|R1LD
LCELL        8         |risel:128|R2LD
LCELL        8         |risel:128|R3LD
LCELL        8         |risel:128|R4LD
INPUT        7         CDUCLK
LCELL        7         :49
LCELL        7         :58


Device-Specific Information:                         d:\computer\alu\alu22.rpt
alu22

** EQUATIONS **

ALU-BUS  : INPUT;
CDUCLK   : INPUT;
CLR      : INPUT;
CN       : INPUT;
DR0      : INPUT;
DR1      : INPUT;
DR2      : INPUT;
DR3      : INPUT;
EN       : INPUT;
LDDR1    : INPUT;
LDDR2    : INPUT;
LDRI     : INPUT;
M        : INPUT;
MUL      : INPUT;
RI-BUS   : INPUT;
SELRI    : INPUT;
SIGNAL   : INPUT;
SW-BUS   : INPUT;
S0       : INPUT;
S1       : INPUT;
S2       : INPUT;
S3       : INPUT;
T2       : INPUT;

-- Node name is 'L1' 
-- Equation name is 'L1', type is bidir 
L1       = TRI(_LC4_B17,  _LC1_A21);

-- Node name is 'L2' 
-- Equation name is 'L2', type is bidir 
L2       = TRI(_LC2_B24,  _LC1_A21);

-- Node name is 'L3' 
-- Equation name is 'L3', type is bidir 
L3       = TRI(_LC5_B22,  _LC1_A21);

-- Node name is 'L4' 
-- Equation name is 'L4', type is bidir 
L4       = TRI(_LC7_B19,  _LC1_A21);

-- Node name is 'L5' 
-- Equation name is 'L5', type is bidir 
L5       = TRI(_LC1_B20,  _LC1_A21);

-- Node name is 'L6' 
-- Equation name is 'L6', type is bidir 
L6       = TRI(_LC2_B16,  _LC1_A21);

-- Node name is 'L7' 
-- Equation name is 'L7', type is bidir 
L7       = TRI(_LC8_B15,  _LC1_A21);

-- Node name is 'L8' 
-- Equation name is 'L8', type is bidir 
L8       = TRI(_LC2_A21,  _LC1_A21);

-- Node name is 'Q1' 
-- Equation name is 'Q1', type is output 
Q1       =  _LC8_B17;

-- Node name is 'Q2' 
-- Equation name is 'Q2', type is output 
Q2       =  _LC3_B17;

-- Node name is 'Q3' 
-- Equation name is 'Q3', type is output 
Q3       =  _LC8_B14;

-- Node name is 'Q4' 
-- Equation name is 'Q4', type is output 
Q4       =  _LC1_B14;

-- Node name is 'Q5' 
-- Equation name is 'Q5', type is output 
Q5       =  _LC2_B14;

-- Node name is 'Q6' 
-- Equation name is 'Q6', type is output 
Q6       =  _LC5_B14;

-- Node name is 'Q7' 
-- Equation name is 'Q7', type is output 
Q7       =  _LC3_B14;

-- Node name is '|cdu:97|cdu16:1|74163:1|f74163:sub|:34' = '|cdu:97|cdu16:1|74163:1|f74163:sub|QA' 
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = DFFE( _EQ001, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ001 =  CLR &  _LC2_B14 & !_LC6_B14
         #  CLR & !_LC2_B14 &  _LC6_B14;

-- Node name is '|cdu:97|cdu16:1|74163:1|f74163:sub|:111' = '|cdu:97|cdu16:1|74163:1|f74163:sub|QB' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = DFFE( _EQ002, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ002 =  CLR & !_LC2_B14 &  _LC5_B14
         #  CLR &  _LC5_B14 & !_LC6_B14
         #  CLR &  _LC2_B14 & !_LC5_B14 &  _LC6_B14;

-- Node name is '|cdu:97|cdu16:1|74163:1|f74163:sub|:122' = '|cdu:97|cdu16:1|74163:1|f74163:sub|QC' 
-- Equation name is '_LC3_B14', type is buried 
_LC3_B14 = DFFE( _EQ003, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ003 =  CLR &  _LC3_B14 & !_LC5_B14
         #  CLR &  _LC3_B14 & !_LC7_B14
         #  CLR & !_LC3_B14 &  _LC5_B14 &  _LC7_B14;

-- Node name is '|cdu:97|cdu16:1|74163:1|f74163:sub|:108' 
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ004);
  _EQ004 =  _LC2_B14 &  _LC6_B14;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:34' = '|cdu:97|cdu16:2|74163:1|f74163:sub|QA' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = DFFE( _EQ005, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ005 =  CLR & !EN &  _LC8_B17
         #  CLR &  EN & !_LC8_B17;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:111' = '|cdu:97|cdu16:2|74163:1|f74163:sub|QB' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = DFFE( _EQ006, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ006 =  CLR &  _LC3_B17 & !_LC8_B17
         #  CLR & !EN &  _LC3_B17
         #  CLR &  EN & !_LC3_B17 &  _LC8_B17;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:122' = '|cdu:97|cdu16:2|74163:1|f74163:sub|QC' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = DFFE( _EQ007, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ007 =  CLR & !_LC5_B17 &  _LC8_B14
         #  CLR & !EN &  _LC8_B14
         #  CLR &  EN &  _LC5_B17 & !_LC8_B14;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:134' = '|cdu:97|cdu16:2|74163:1|f74163:sub|QD' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = DFFE( _EQ008, GLOBAL( CDUCLK),  VCC,  VCC,  VCC);
  _EQ008 =  CLR &  _LC1_B14 & !_LC4_B14
         #  CLR & !EN &  _LC1_B14
         #  CLR &  EN & !_LC1_B14 &  _LC4_B14;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:106' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = LCELL( _EQ009);
  _EQ009 =  EN &  _LC3_B17 &  _LC8_B17;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:117' 
-- Equation name is '_LC4_B14', type is buried 
_LC4_B14 = LCELL( _EQ010);
  _EQ010 =  _LC5_B17 &  _LC8_B14;

-- Node name is '|cdu:97|cdu16:2|74163:1|f74163:sub|:128' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ011);
  _EQ011 =  _LC1_B14 &  _LC5_B17 &  _LC8_B14;

-- Node name is '|MULTI:42|one_bit_adder:U_0_0|:7' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = LCELL( _EQ012);
  _EQ012 = !_LC2_B2 &  _LC6_B8 &  _LC7_B2
         # !_LC4_B8 &  _LC6_B8 &  _LC7_B2
         #  _LC2_B2 &  _LC4_B8 & !_LC6_B8
         #  _LC2_B2 &  _LC4_B8 & !_LC7_B2;

-- Node name is '|MULTI:42|one_bit_adder:U_0_0|:12' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ013);
  _EQ013 =  _LC2_B2 &  _LC4_B8 &  _LC6_B8 &  _LC7_B2;

-- Node name is '|MULTI:42|one_bit_adder:U_0_1|:8' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ014);
  _EQ014 = !_LC2_B7 & !_LC4_B4 &  _LC4_B8 &  _LC7_B2
         # !_LC2_B7 &  _LC4_B4 & !_LC7_B2
         # !_LC2_B7 &  _LC4_B4 & !_LC4_B8
         #  _LC2_B7 &  _LC4_B4 &  _LC4_B8 &  _LC7_B2
         #  _LC2_B7 & !_LC4_B4 & !_LC7_B2
         #  _LC2_B7 & !_LC4_B4 & !_LC4_B8;

-- Node name is '|MULTI:42|one_bit_adder:U_0_1|:12' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ015);
  _EQ015 =  _LC3_B2 &  _LC4_B8 &  _LC6_B8 &  _LC7_B2;

-- Node name is '|MULTI:42|one_bit_adder:U_0_1|:15' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ016);
  _EQ016 =  _LC3_B4
         # !_LC3_B2 &  _LC4_B4;

-- Node name is '|MULTI:42|one_bit_adder:U_0_2|:8' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ017);
  _EQ017 = !_LC3_B2 &  _LC4_B4 & !_LC7_B4
         #  _LC3_B4 & !_LC7_B4
         #  _LC3_B2 & !_LC3_B4 &  _LC7_B4
         # !_LC3_B4 & !_LC4_B4 &  _LC7_B4;

-- Node name is '|MULTI:42|one_bit_adder:U_0_2|:13' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ018);
  _EQ018 =  _LC3_B2 &  _LC4_B8 & !_LC6_B8
         #  _LC3_B2 & !_LC4_B2 &  _LC4_B8
         #  _LC4_B2 & !_LC4_B8 &  _LC6_B8
         # !_LC3_B2 &  _LC4_B2 &  _LC6_B8;

-- Node name is '|MULTI:42|one_bit_adder:U_0_2|:15' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ019);
  _EQ019 =  _LC5_B4 &  _LC7_B4

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