alu22.rpt
来自「vhd语言」· RPT 代码 · 共 1,381 行 · 第 1/5 页
RPT
1,381 行
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 8 ALU-BUS
1 - - - -- INPUT G 0 0 0 0 CDUCLK
79 - - - 24 INPUT 0 0 0 7 CLR
11 - - - 01 INPUT 0 0 0 2 CN
17 - - A -- INPUT 0 0 0 1 DR0
18 - - A -- INPUT 0 0 0 1 DR1
70 - - A -- INPUT 0 0 0 1 DR2
73 - - A -- INPUT 0 0 0 1 DR3
80 - - - 23 INPUT 0 0 0 5 EN
35 - - - 06 INPUT 0 0 0 1 LDDR1
21 - - B -- INPUT 0 0 0 1 LDDR2
69 - - A -- INPUT 0 0 0 4 LDRI
50 - - - 17 BIDIR 0 1 0 6 L1
22 - - B -- BIDIR 0 1 0 6 L2
24 - - B -- BIDIR 0 1 0 6 L3
64 - - B -- BIDIR 0 1 0 6 L4
67 - - B -- BIDIR 0 1 0 6 L5
48 - - - 15 BIDIR 0 1 0 6 L6
25 - - B -- BIDIR 0 1 0 6 L7
81 - - - 22 BIDIR 0 1 0 4 L8
84 - - - -- INPUT 0 0 0 7 M
2 - - - -- INPUT 0 0 0 10 MUL
71 - - A -- INPUT 0 0 0 7 RI-BUS
72 - - A -- INPUT 0 0 0 2 SELRI
16 - - A -- INPUT 0 0 0 1 SIGNAL
42 - - - -- INPUT 0 0 0 8 SW-BUS
10 - - - 01 INPUT 0 0 0 7 S0
43 - - - -- INPUT 0 0 0 7 S1
8 - - - 03 INPUT 0 0 0 7 S2
36 - - - 07 INPUT 0 0 0 7 S3
5 - - - 05 INPUT 0 0 0 6 T2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\computer\alu\alu22.rpt
alu22
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
50 - - - 17 TRI 0 1 0 6 L1
22 - - B -- TRI 0 1 0 6 L2
24 - - B -- TRI 0 1 0 6 L3
64 - - B -- TRI 0 1 0 6 L4
67 - - B -- TRI 0 1 0 6 L5
48 - - - 15 TRI 0 1 0 6 L6
25 - - B -- TRI 0 1 0 6 L7
81 - - - 22 TRI 0 1 0 4 L8
51 - - - 18 OUTPUT 0 1 0 0 Q1
28 - - C -- OUTPUT 0 1 0 0 Q2
83 - - - 13 OUTPUT 0 1 0 0 Q3
47 - - - 14 OUTPUT 0 1 0 0 Q4
66 - - B -- OUTPUT 0 1 0 0 Q5
65 - - B -- OUTPUT 0 1 0 0 Q6
23 - - B -- OUTPUT 0 1 0 0 Q7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\alu22.rpt
alu22
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 14 DFFE + 1 1 1 3 |cdu:97|cdu16:1|74163:1|f74163:sub|QA (|cdu:97|cdu16:1|74163:1|f74163:sub|:34)
- 7 - B 14 AND2 0 2 0 1 |cdu:97|cdu16:1|74163:1|f74163:sub|:108
- 5 - B 14 DFFE + 1 2 1 2 |cdu:97|cdu16:1|74163:1|f74163:sub|QB (|cdu:97|cdu16:1|74163:1|f74163:sub|:111)
- 3 - B 14 DFFE + 1 2 1 1 |cdu:97|cdu16:1|74163:1|f74163:sub|QC (|cdu:97|cdu16:1|74163:1|f74163:sub|:122)
- 8 - B 17 DFFE + 2 0 1 3 |cdu:97|cdu16:2|74163:1|f74163:sub|QA (|cdu:97|cdu16:2|74163:1|f74163:sub|:34)
- 5 - B 17 AND2 1 2 0 3 |cdu:97|cdu16:2|74163:1|f74163:sub|:106
- 3 - B 17 DFFE + 2 1 1 2 |cdu:97|cdu16:2|74163:1|f74163:sub|QB (|cdu:97|cdu16:2|74163:1|f74163:sub|:111)
- 4 - B 14 AND2 0 2 0 1 |cdu:97|cdu16:2|74163:1|f74163:sub|:117
- 8 - B 14 DFFE + 2 1 1 3 |cdu:97|cdu16:2|74163:1|f74163:sub|QC (|cdu:97|cdu16:2|74163:1|f74163:sub|:122)
- 6 - B 14 AND2 0 3 0 3 |cdu:97|cdu16:2|74163:1|f74163:sub|:128
- 1 - B 14 DFFE + 2 1 1 2 |cdu:97|cdu16:2|74163:1|f74163:sub|QD (|cdu:97|cdu16:2|74163:1|f74163:sub|:134)
- 5 - B 24 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_0_0|:7
- 4 - B 04 AND2 0 4 0 3 |MULTI:42|one_bit_adder:U_0_0|:12
- 6 - B 04 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_1|:8
- 3 - B 04 AND2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_1|:12
- 5 - B 04 OR2 0 3 0 1 |MULTI:42|one_bit_adder:U_0_1|:15
- 2 - B 04 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_2|:8
- 7 - B 04 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_2|:13
- 1 - B 04 OR2 0 3 0 4 |MULTI:42|one_bit_adder:U_0_2|:15
- 4 - B 05 OR2 0 4 0 4 |MULTI:42|one_bit_adder:U_0_3|:13
- 5 - B 05 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_4|:8
- 6 - B 05 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_0_4|:13
- 7 - B 05 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_0_4|:14
- 8 - B 22 AND2 0 3 0 2 |MULTI:42|one_bit_adder:U_1_0|:12
- 8 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_1|:8
- 3 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_1|:15
- 6 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_2|:8
- 2 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_2|:15
- 4 - B 10 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_1_3|:8
- 3 - B 10 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_1_3|:15
- 7 - B 12 AND2 0 3 0 2 |MULTI:42|one_bit_adder:U_2_0|:12
- 4 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_2_1|:8
- 1 - B 12 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_2_1|:15
- 6 - B 10 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_2_2|:8
- 5 - B 10 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_2_2|:15
- 7 - B 10 AND2 0 3 0 2 |MULTI:42|one_bit_adder:U_3_0|:12
- 2 - B 10 OR2 0 4 0 2 |MULTI:42|one_bit_adder:U_3_1|:8
- 8 - B 10 OR2 0 4 0 1 |MULTI:42|one_bit_adder:U_3_1|:15
- 1 - B 03 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~1
- 2 - B 05 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~2
- 1 - B 05 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~3
- 1 - B 10 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~4
- 1 - B 16 OR2 s 0 4 0 1 |MULTI:42|one_bit_adder:U_4_1|~8~5
- 2 - B 07 AND2 0 2 0 1 |MULTI:42|:1401
- 5 - B 12 AND2 0 2 0 2 |MULTI:42|:1716
- 4 - B 19 AND2 0 2 0 1 |MULTI:42|:1830
- 6 - A 15 OR2 3 0 0 6 |risel:128|2sel1:17|Y1 (|risel:128|2sel1:17|:101)
- 5 - A 15 OR2 ! 3 0 0 6 |risel:128|2sel1:17|Y2 (|risel:128|2sel1:17|:102)
- 2 - A 15 OR2 0 2 0 3 |risel:128|4sel1:12|:8
- 4 - A 13 AND2 2 2 0 8 |risel:128|R1LD (|risel:128|:8)
- 8 - A 13 AND2 2 2 0 8 |risel:128|R2LD (|risel:128|:9)
- 3 - A 13 AND2 2 1 0 8 |risel:128|R3LD (|risel:128|:10)
- 2 - A 13 AND2 3 0 0 8 |risel:128|R4LD (|risel:128|:11)
- 3 - A 15 OR2 ! 1 2 0 8 |risel:128|:19
- 4 - A 15 OR2 ! 1 2 0 8 |risel:128|:20
- 1 - A 13 OR2 ! 1 1 0 7 |risel:128|:21
- 1 - A 15 OR2 ! 1 2 0 8 |risel:128|:22
- 6 - B 02 AND2 2 0 0 7 :49
- 2 - B 08 AND2 2 0 0 7 :58
- 3 - B 09 OR2 ! 2 2 0 2 |74181:98|:43
- 4 - B 06 OR2 ! 2 2 0 3 |74181:98|:44
- 7 - B 06 OR2 ! 2 2 0 2 |74181:98|:45
- 4 - B 09 OR2 ! 2 2 0 2 |74181:98|:46
- 5 - B 06 OR2 ! 2 2 0 3 |74181:98|:47
- 7 - B 03 OR2 ! 2 2 0 2 |74181:98|:48
- 6 - B 03 OR2 ! 2 2 0 3 |74181:98|:51
- 8 - B 03 OR2 ! 2 2 0 3 |74181:98|:52
- 8 - B 06 OR2 1 3 0 1 |74181:98|:75
- 3 - B 11 OR2 1 3 0 1 |74181:98|:77
- 8 - B 09 OR2 s 1 2 0 3 |74181:98|CN4~1 (|74181:98|~78~1)
- 6 - B 06 OR2 s 0 2 0 1 |74181:98|CN4~2 (|74181:98|~78~2)
- 3 - B 06 OR2 s 0 4 0 3 |74181:98|CN4~3 (|74181:98|~78~3)
- 1 - B 09 OR2 2 2 0 1 |74181:98|:80
- 1 - B 06 OR2 1 3 0 1 |74181:98|:81
- 4 - B 03 OR2 ! 2 2 0 3 |74181:99|:43
- 5 - B 03 OR2 ! 2 2 0 2 |74181:99|:44
- 2 - B 09 OR2 2 2 0 1 |74181:99|:45
- 3 - B 03 OR2 ! 2 2 0 2 |74181:99|:46
- 2 - B 03 OR2 ! 2 2 0 2 |74181:99|:47
- 5 - B 09 OR2 2 2 0 1 |74181:99|:48
- 7 - B 11 OR2 1 3 0 1 |74181:99|:64
- 2 - B 11 OR2 s 0 4 0 2 |74181:99|~69~1
- 1 - B 11 OR2 s 0 4 0 1 |74181:99|~75~1
- 4 - B 11 OR2 1 2 0 1 |74181:99|:79
- 4 - B 15 OR2 1 3 0 1 |74181:99|:82
- 5 - A 13 OR2 s 0 4 0 1 |74244:109|~1~1~3~2
- 1 - A 24 OR2 s 0 3 0 1 |74244:109|~1~1~3~3
- 2 - B 17 OR2 s 2 2 0 1 |74244:109|~1~1~3~4
- 4 - B 17 OR2 0 4 1 0 |74244:109|~1~1~3
- 1 - B 17 OR2 s 1 3 0 1 |74244:109|~1~2~1
- 1 - B 24 OR2 s 0 4 0 1 |74244:109|~6~1~3~2
- 3 - B 24 OR2 s 1 3 0 1 |74244:109|~6~1~3~3
- 4 - B 24 OR2 s 0 3 0 1 |74244:109|~6~1~3~4
- 2 - B 24 AND2 0 3 1 0 |74244:109|~6~1~3
- 6 - B 24 OR2 2 2 0 1 |74244:109|~6~2
- 1 - B 22 OR2 s 0 4 0 1 |74244:109|~10~1~3~2
- 1 - B 18 OR2 s 1 3 0 1 |74244:109|~10~1~3~3
- 2 - B 22 OR2 s 0 4 0 1 |74244:109|~10~1~3~4
- 5 - B 22 OR2 1 3 1 0 |74244:109|~10~1~3
- 1 - B 19 OR2 s 0 4 0 1 |74244:109|~11~1~3~2
- 2 - B 19 OR2 s 1 3 0 1 |74244:109|~11~1~3~3
- 3 - B 19 OR2 s 0 3 0 1 |74244:109|~11~1~3~4
- 7 - B 19 OR2 1 3 1 0 |74244:109|~11~1~3
- 5 - B 19 OR2 s 1 3 0 1 |74244:109|~11~2~1
- 3 - A 21 OR2 s ! 2 0 0 2 |74244:109|~26~1~3~2
- 4 - A 21 OR2 s 1 3 0 1 |74244:109|~26~1~3~3
- 5 - A 21 OR2 s 1 3 0 1 |74244:109|~26~1~3~4
- 6 - A 21 OR2 s 0 3 0 1 |74244:109|~26~1~3~5
- 2 - A 21 OR2 0 3 1 0 |74244:109|~26~1~3
- 1 - A 21 OR2 1 1 0 0 |74244:109|~27~1~2
- 1 - B 15 OR2 s 1 3 0 1 |74244:109|~27~1~3~2
- 2 - B 15 OR2 s 0 3 0 1 |74244:109|~27~1~3~3
- 3 - B 15 OR2 s 0 4 0 1 |74244:109|~27~1~3~4
- 8 - B 15 OR2 1 3 1 0 |74244:109|~27~1~3
- 5 - B 15 OR2 s 1 3 0 1 |74244:109|~27~2~1
- 4 - B 16 OR2 s 0 4 0 1 |74244:109|~31~1~3~2
- 5 - B 16 OR2 s 1 3 0 1 |74244:109|~31~1~3~3
- 6 - B 16 OR2 s 0 4 0 1 |74244:109|~31~1~3~4
- 2 - B 16 OR2 1 3 1 0 |74244:109|~31~1~3
- 2 - B 23 OR2 s 0 4 0 1 |74244:109|~36~1~3~2
- 3 - B 20 OR2 s 1 3 0 1 |74244:109|~36~1~3~3
- 4 - B 20 OR2 s 0 4 0 1 |74244:109|~36~1~3~4
- 1 - B 20 OR2 1 3 1 0 |74244:109|~36~1~3
- 3 - B 22 OR2 1 3 0 1 |74257:100|:6
- 2 - B 06 OR2 1 3 0 1 |74257:100|:35
- 2 - B 20 OR2 1 3 0 1 |74257:101|:2
- 3 - B 16 OR2 1 3 0 1 |74257:101|:4
- 5 - B 11 OR2 1 3 0 1 |74257:101|:33
- 6 - B 11 OR2 1 3 0 1 |74257:101|:34
- 6 - B 09 DFFE 0 2 0 2 |74273:102|Q7 (|74273:102|:13)
- 8 - B 05 AND2 s 0 4 0 1 |74273:102|Q6~1 (|74273:102|~14~1)
- 1 - B 02 DFFE 0 2 0 5 |74273:102|Q6 (|74273:102|:14)
- 3 - B 05 AND2 s 0 4 0 2 |74273:102|Q5~1 (|74273:102|~15~1)
- 5 - B 02 DFFE 0 2 0 7 |74273:102|Q5 (|74273:102|:15)
- 8 - B 04 AND2 s 0 4 0 1 |74273:102|Q4~1 (|74273:102|~16~1)
- 4 - B 02 DFFE 0 2 0 9 |74273:102|Q4 (|74273:102|:16)
- 3 - B 02 DFFE 0 2 0 12 |74273:102|Q3 (|74273:102|:17)
- 7 - B 02 DFFE 0 2 0 13 |74273:102|Q2 (|74273:102|:18)
- 2 - B 02 DFFE 0 2 0 13 |74273:102|Q1 (|74273:102|:19)
- 7 - B 09 DFFE 0 2 0 2 |74273:103|Q7 (|74273:103|:13)
- 7 - B 08 DFFE 0 2 0 4 |74273:103|Q6 (|74273:103|:14)
- 5 - B 08 DFFE 0 2 0 7 |74273:103|Q5 (|74273:103|:15)
- 3 - B 08 DFFE 0 2 0 9 |74273:103|Q4 (|74273:103|:16)
- 8 - B 08 DFFE 0 2 0 10 |74273:103|Q3 (|74273:103|:17)
- 4 - B 08 DFFE 0 2 0 13 |74273:103|Q2 (|74273:103|:18)
- 6 - B 08 DFFE 0 2 0 13 |74273:103|Q1 (|74273:103|:19)
- 6 - B 17 DFFE 0 2 0 1 |74374:105|:13
- 8 - B 24 DFFE 0 2 0 1 |74374:105|:14
- 6 - B 22 DFFE 0 2 0 1 |74374:105|:15
- 8 - B 19 DFFE 0 2 0 1 |74374:105|:16
- 3 - B 23 DFFE 0 2 0 1 |74374:105|:17
- 4 - A 22 DFFE 0 2 0 1 |74374:105|:18
- 7 - B 15 DFFE 0 2 0 1 |74374:105|:19
- 8 - A 21 DFFE 0 2 0 1 |74374:105|:20
- 2 - A 24 DFFE 0 2 0 1 |74374:106|:13
- 7 - B 24 DFFE 0 2 0 1 |74374:106|:14
- 4 - B 22 DFFE 0 2 0 1 |74374:106|:15
- 6 - B 19 DFFE 0 2 0 1 |74374:106|:16
- 1 - B 23 DFFE 0 2 0 1 |74374:106|:17
- 7 - B 16 DFFE 0 2 0 1 |74374:106|:18
- 6 - B 15 DFFE 0 2 0 1 |74374:106|:19
- 7 - A 21 DFFE 0 2 0 1 |74374:106|:20
- 7 - A 13 DFFE 0 2 0 1 |74374:107|:13
- 3 - B 21 DFFE 0 2 0 1 |74374:107|:14
- 2 - B 01 DFFE 0 2 0 1 |74374:107|:15
- 4 - B 21 DFFE 0 2 0 1 |74374:107|:16
- 6 - B 20 DFFE 0 2 0 1 |74374:107|:17
- 8 - B 16 DFFE 0 2 0 1 |74374:107|:18
- 1 - B 21 DFFE 0 2 0 1 |74374:107|:19
- 7 - B 21 DFFE 0 2 0 1 |74374:107|:20
- 6 - A 13 DFFE 0 2 0 1 |74374:108|:13
- 5 - B 21 DFFE 0 2 0 1 |74374:108|:14
- 2 - B 18 DFFE 0 2 0 1 |74374:108|:15
- 2 - B 21 DFFE 0 2 0 1 |74374:108|:16
- 5 - B 20 DFFE 0 2 0 1 |74374:108|:17
- 8 - B 13 DFFE 0 2 0 1 |74374:108|:18
- 8 - B 21 DFFE 0 2 0 1 |74374:108|:19
- 6 - B 21 DFFE 0 2 0 1 |74374:108|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
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