📄 alu.rpt
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- 1 - A 18 OR2 s 0 4 0 1 |MULTI:94|one_bit_adder:U_4_1|~8~2
- 2 - A 18 OR2 s 0 4 0 1 |MULTI:94|one_bit_adder:U_4_1|~8~3
- 6 - A 15 OR2 s 0 4 0 1 |MULTI:94|one_bit_adder:U_4_1|~8~4
- 8 - A 15 OR2 0 4 0 1 |MULTI:94|one_bit_adder:U_4_1|:8
- 1 - A 13 AND2 0 2 0 1 |MULTI:94|:1401
- 8 - A 20 AND2 0 2 0 2 |MULTI:94|:1716
- 5 - B 20 OR2 ! 3 0 0 4 |2sel1:261|Y1 (|2sel1:261|:101)
- 7 - B 20 OR2 3 1 0 2 |4sel1:293|Y0N (|4sel1:293|:6)
- 2 - B 20 OR2 3 1 0 2 |4sel1:293|Y1N (|4sel1:293|:7)
- 6 - B 20 OR2 3 1 0 2 |4sel1:293|Y2N (|4sel1:293|:8)
- 1 - B 20 OR2 3 1 0 9 |4sel1:293|Y3N (|4sel1:293|:9)
- 4 - A 17 AND2 2 0 0 7 :66
- 4 - C 17 AND2 2 0 0 7 :93
- 2 - B 10 AND2 2 0 0 8 :139
- 3 - B 10 AND2 2 0 0 8 :140
- 3 - B 20 AND2 2 1 0 8 :253
- 4 - B 20 AND2 1 1 0 8 :254
- 4 - B 14 AND2 2 1 0 8 :255
- 2 - B 17 AND2 2 1 0 8 :257
- 4 - B 17 AND2 1 1 0 8 :258
- 3 - B 17 AND2 2 1 0 8 :259
- 6 - B 17 AND2 1 1 0 8 :260
- 7 - B 06 DFFE 1 3 0 4 |74161:134|f74161:sub|QA (|74161:134|f74161:sub|:9)
- 6 - B 06 AND2 0 2 0 1 |74161:134|f74161:sub|:80
- 5 - B 06 AND2 0 3 0 1 |74161:134|f74161:sub|:84
- 2 - B 06 DFFE 1 3 0 3 |74161:134|f74161:sub|QB (|74161:134|f74161:sub|:87)
- 8 - B 06 AND2 0 4 0 1 |74161:134|f74161:sub|:94
- 1 - B 06 DFFE 1 3 0 2 |74161:134|f74161:sub|QC (|74161:134|f74161:sub|:99)
- 4 - B 06 DFFE 1 3 0 1 |74161:134|f74161:sub|QD (|74161:134|f74161:sub|:110)
- 8 - B 01 DFFE 1 2 0 4 |74161:135|f74161:sub|QA (|74161:135|f74161:sub|:9)
- 1 - B 01 AND2 0 2 0 1 |74161:135|f74161:sub|:84
- 7 - B 01 DFFE 1 3 0 3 |74161:135|f74161:sub|QB (|74161:135|f74161:sub|:87)
- 3 - B 01 AND2 0 3 0 2 |74161:135|f74161:sub|:94
- 5 - B 01 DFFE 1 3 0 2 |74161:135|f74161:sub|QC (|74161:135|f74161:sub|:99)
- 6 - B 11 AND2 0 2 0 4 |74161:135|f74161:sub|:104
- 3 - B 11 DFFE 1 3 0 2 |74161:135|f74161:sub|QD (|74161:135|f74161:sub|:110)
- 2 - A 19 OR2 ! 2 2 0 2 |74181:1|:43
- 1 - A 23 OR2 ! 2 2 0 2 |74181:1|:44
- 7 - A 19 OR2 ! 2 2 0 2 |74181:1|:45
- 6 - A 19 OR2 ! 2 2 0 2 |74181:1|:46
- 2 - A 23 OR2 ! 2 2 0 2 |74181:1|:47
- 4 - A 19 OR2 ! 2 2 0 2 |74181:1|:48
- 5 - A 19 OR2 ! 2 2 0 2 |74181:1|:51
- 3 - A 19 OR2 ! 2 2 0 2 |74181:1|:52
- 3 - A 03 OR2 1 3 0 1 |74181:1|:77
- 1 - A 19 OR2 s 1 2 0 2 |74181:1|CN4~1 (|74181:1|~78~1)
- 7 - A 23 OR2 s 0 3 0 2 |74181:1|CN4~2 (|74181:1|~78~2)
- 7 - A 13 OR2 s 0 3 0 2 |74181:1|CN4~3 (|74181:1|~78~3)
- 1 - A 03 OR2 ! 0 3 0 2 |74181:1|CN4 (|74181:1|:78)
- 8 - A 19 OR2 2 2 0 1 |74181:1|:80
- 3 - A 23 OR2 1 3 0 1 |74181:1|:81
- 4 - A 13 OR2 1 3 0 1 |74181:1|:82
- 3 - A 14 OR2 ! 2 2 0 2 |74181:2|:43
- 2 - A 14 OR2 ! 2 2 0 2 |74181:2|:44
- 2 - A 16 OR2 s 2 1 0 1 |74181:2|~45~1
- 5 - A 14 OR2 ! 2 2 0 2 |74181:2|:46
- 8 - A 14 OR2 ! 2 2 0 2 |74181:2|:47
- 3 - A 16 OR2 s 2 1 0 1 |74181:2|~48~1
- 6 - A 14 OR2 s 0 3 0 2 |74181:2|~75~1
- 4 - A 14 OR2 1 3 0 1 |74181:2|:75
- 1 - A 14 OR2 1 3 0 1 |74181:2|:80
- 7 - A 14 OR2 1 3 0 1 |74181:2|:81
- 4 - A 16 OR2 0 4 0 1 |74181:2|:82
- 1 - A 24 OR2 s 1 3 0 1 |74244:106|~1~1~1
- 4 - A 23 OR2 2 2 0 1 |74244:106|~6~1
- 6 - A 13 OR2 2 2 0 1 |74244:106|~10~1
- 4 - A 03 OR2 2 2 0 1 |74244:106|~11~1
- 5 - A 16 OR2 2 2 0 1 |74244:106|~27~1
- 1 - A 01 OR2 2 2 0 1 |74244:106|~31~1
- 1 - A 11 OR2 2 2 0 1 |74244:106|~36~1
- 2 - A 24 OR2 s 1 3 0 1 |74244:142|~1~1~1~2
- 6 - B 01 OR2 s 2 2 0 1 |74244:142|~1~1~1~3
- 3 - A 24 OR2 s 0 3 0 1 |74244:142|~1~1~1~4
- 6 - A 24 OR2 s 0 4 0 1 |74244:142|~1~1~1~5
- 4 - A 24 OR2 1 3 1 9 |74244:142|~1~1~1
- 2 - B 01 OR2 s 2 2 0 1 |74244:142|~6~1~1~2
- 4 - B 24 OR2 s 0 3 0 1 |74244:142|~6~1~1~3
- 2 - B 22 OR2 s 0 4 0 1 |74244:142|~6~1~1~4
- 3 - B 22 OR2 s 0 3 0 1 |74244:142|~6~1~1~5
- 1 - B 22 OR2 1 3 1 9 |74244:142|~6~1~1
- 4 - B 01 OR2 s 2 2 0 1 |74244:142|~10~1~1~2
- 2 - B 11 OR2 s 0 3 0 1 |74244:142|~10~1~1~3
- 2 - A 06 OR2 s 0 4 0 1 |74244:142|~10~1~1~4
- 3 - A 06 OR2 s 0 3 0 1 |74244:142|~10~1~1~5
- 4 - A 06 OR2 1 3 1 9 |74244:142|~10~1~1
- 1 - B 11 OR2 s 2 2 0 1 |74244:142|~11~1~1~2
- 5 - B 11 OR2 s 0 3 0 1 |74244:142|~11~1~1~3
- 5 - A 03 OR2 s 0 4 0 1 |74244:142|~11~1~1~4
- 6 - A 03 OR2 s 0 3 0 1 |74244:142|~11~1~1~5
- 2 - A 03 OR2 1 3 1 9 |74244:142|~11~1~1
- 1 - B 16 OR2 s 0 4 0 1 |74244:142|~26~1~1~2
- 1 - B 08 OR2 s 3 0 0 1 |74244:142|~26~1~1~3
- 8 - B 08 OR2 s 1 2 0 1 |74244:142|~26~1~1~4
- 2 - B 24 OR2 s 1 3 0 1 |74244:142|~26~1~1~5
- 7 - B 24 OR2 0 4 1 6 |74244:142|~26~1~1
- 4 - B 12 OR2 s 2 2 0 1 |74244:142|~27~1~1~2
- 8 - B 12 OR2 s 0 3 0 1 |74244:142|~27~1~1~3
- 1 - B 17 OR2 s 0 4 0 1 |74244:142|~27~1~1~4
- 8 - B 17 OR2 s 0 3 0 1 |74244:142|~27~1~1~5
- 1 - A 16 OR2 1 3 1 9 |74244:142|~27~1~1
- 5 - B 12 OR2 s 2 2 0 1 |74244:142|~31~1~1~2
- 1 - B 12 OR2 s 0 3 0 1 |74244:142|~31~1~1~3
- 3 - A 01 OR2 s 0 4 0 1 |74244:142|~31~1~1~4
- 4 - A 01 OR2 s 0 3 0 1 |74244:142|~31~1~1~5
- 2 - A 01 OR2 1 3 1 9 |74244:142|~31~1~1
- 3 - B 06 OR2 s 2 2 0 1 |74244:142|~36~1~1~2
- 4 - B 04 OR2 s 0 3 0 1 |74244:142|~36~1~1~3
- 2 - A 11 OR2 s 0 4 0 1 |74244:142|~36~1~1~4
- 3 - A 11 OR2 s 0 3 0 1 |74244:142|~36~1~1~5
- 7 - A 11 OR2 1 3 1 9 |74244:142|~36~1~1
- 2 - A 17 DFFE 0 2 0 1 |74273:5|Q7 (|74273:5|:13)
- 5 - A 18 AND2 s 0 4 0 1 |74273:5|Q6~1 (|74273:5|~14~1)
- 3 - A 17 DFFE 0 2 0 5 |74273:5|Q6 (|74273:5|:14)
- 3 - A 21 AND2 s 0 4 0 2 |74273:5|Q5~1 (|74273:5|~15~1)
- 7 - A 17 DFFE 0 2 0 7 |74273:5|Q5 (|74273:5|:15)
- 7 - A 21 AND2 s 0 4 0 1 |74273:5|Q4~1 (|74273:5|~16~1)
- 5 - A 17 DFFE 0 2 0 9 |74273:5|Q4 (|74273:5|:16)
- 6 - A 17 DFFE 0 2 0 12 |74273:5|Q3 (|74273:5|:17)
- 8 - A 17 DFFE 0 2 0 13 |74273:5|Q2 (|74273:5|:18)
- 1 - A 17 DFFE 0 2 0 14 |74273:5|Q1 (|74273:5|:19)
- 6 - A 16 DFFE 0 2 0 2 |74273:6|Q7 (|74273:6|:13)
- 7 - A 15 DFFE 0 2 0 4 |74273:6|Q6 (|74273:6|:14)
- 6 - A 21 DFFE 0 2 0 7 |74273:6|Q5 (|74273:6|:15)
- 5 - A 21 DFFE 0 2 0 9 |74273:6|Q4 (|74273:6|:16)
- 1 - A 12 DFFE 0 2 0 10 |74273:6|Q3 (|74273:6|:17)
- 8 - A 21 DFFE 0 2 0 13 |74273:6|Q2 (|74273:6|:18)
- 2 - A 21 DFFE 0 2 0 13 |74273:6|Q1 (|74273:6|:19)
- 5 - B 10 DFFE 0 2 0 1 |74273:141|Q8 (|74273:141|:12)
- 7 - B 10 DFFE 0 2 0 1 |74273:141|Q7 (|74273:141|:13)
- 8 - B 10 DFFE 0 2 0 1 |74273:141|Q6 (|74273:141|:14)
- 1 - A 05 DFFE 0 2 0 1 |74273:141|Q5 (|74273:141|:15)
- 2 - A 05 DFFE 0 2 0 1 |74273:141|Q4 (|74273:141|:16)
- 6 - A 02 DFFE 0 2 0 1 |74273:141|Q3 (|74273:141|:17)
- 7 - A 02 DFFE 0 2 0 1 |74273:141|Q2 (|74273:141|:18)
- 8 - A 02 DFFE 0 2 0 1 |74273:141|Q1 (|74273:141|:19)
- 5 - A 02 LCELL 0 1 1 7 |74373:331|:12
- 3 - A 02 LCELL 0 1 1 7 |74373:331|:13
- 1 - A 02 LCELL 0 1 1 7 |74373:331|:14
- 7 - A 05 LCELL 0 1 1 7 |74373:331|:15
- 3 - A 05 LCELL 0 1 1 7 |74373:331|:16
- 6 - B 10 LCELL 0 1 1 7 |74373:331|:17
- 1 - B 10 LCELL 0 1 1 7 |74373:331|:18
- 4 - B 10 LCELL 0 1 1 7 |74373:331|:19
- 3 - B 24 DFFE 0 2 0 1 |74374:7|:13
- 1 - B 24 DFFE 0 2 0 1 |74374:7|:14
- 4 - B 11 DFFE 0 2 0 1 |74374:7|:15
- 7 - B 11 DFFE 0 2 0 1 |74374:7|:16
- 1 - B 04 DFFE 0 2 0 1 |74374:7|:17
- 8 - B 24 DFFE 0 2 0 1 |74374:7|:18
- 6 - B 12 DFFE 0 2 0 1 |74374:7|:19
- 6 - B 24 DFFE 0 2 0 1 |74374:7|:20
- 7 - A 24 DFFE 0 2 0 1 |74374:8|:13
- 5 - B 22 DFFE 0 2 0 1 |74374:8|:14
- 6 - A 06 DFFE 0 2 0 1 |74374:8|:15
- 8 - A 03 DFFE 0 2 0 1 |74374:8|:16
- 5 - A 11 DFFE 0 2 0 1 |74374:8|:17
- 6 - A 01 DFFE 0 2 0 1 |74374:8|:18
- 7 - B 17 DFFE 0 2 0 1 |74374:8|:19
- 3 - B 16 DFFE 0 2 0 1 |74374:8|:20
- 8 - A 24 DFFE 0 2 0 1 |74374:9|:13
- 4 - B 22 DFFE 0 2 0 1 |74374:9|:14
- 5 - A 06 DFFE 0 2 0 1 |74374:9|:15
- 7 - A 03 DFFE 0 2 0 1 |74374:9|:16
- 4 - A 11 DFFE 0 2 0 1 |74374:9|:17
- 5 - A 01 DFFE 0 2 0 1 |74374:9|:18
- 5 - B 17 DFFE 0 2 0 1 |74374:9|:19
- 2 - B 16 DFFE 0 2 0 1 |74374:9|:20
- 4 - A 02 DFFE 0 2 0 1 |74374:10|:13
- 2 - B 14 DFFE 0 2 0 1 |74374:10|:14
- 2 - A 02 DFFE 0 2 0 1 |74374:10|:15
- 5 - A 10 DFFE 0 2 0 1 |74374:10|:16
- 7 - A 10 DFFE 0 2 0 1 |74374:10|:17
- 4 - A 10 DFFE 0 2 0 1 |74374:10|:18
- 1 - A 10 DFFE 0 2 0 1 |74374:10|:19
- 5 - B 24 DFFE 0 2 0 1 |74374:10|:20
- 5 - A 24 OR2 1 2 0 1 |74374:10|~40~1
- 1 - B 14 OR2 1 2 0 1 |74374:10|~41~1
- 1 - A 06 OR2 1 2 0 1 |74374:10|~42~1
- 8 - A 10 OR2 1 2 0 1 |74374:10|~43~1
- 6 - A 10 OR2 1 2 0 1 |74374:10|~44~1
- 3 - A 10 OR2 1 2 0 1 |74374:10|~45~1
- 2 - A 10 OR2 1 2 0 1 |74374:10|~46~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\alu.rpt
alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 52/ 96( 54%) 20/ 48( 41%) 37/ 48( 77%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 21/ 96( 21%) 21/ 48( 43%) 18/ 48( 37%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 2/ 96( 2%) 3/ 48( 6%) 1/ 48( 2%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\alu.rpt
alu
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 :139
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