📄 shixu.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\maxplus2\multi\cpu\shixu.rpt
shixu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\multi\cpu\shixu.rpt
shixu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 qd
INPUT 3 clk
Device-Specific Information: c:\maxplus2\multi\cpu\shixu.rpt
shixu
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 3 :164
LCELL 2 :190
Device-Specific Information: c:\maxplus2\multi\cpu\shixu.rpt
shixu
** EQUATIONS **
clk : INPUT;
dp : INPUT;
qd : INPUT;
tj : INPUT;
-- Node name is ':13' = 'dan'
-- Equation name is 'dan', location is LC6_C6, type is buried.
dan = DFFE( dp, GLOBAL(!qd), VCC, VCC, !_LC5_C6);
-- Node name is ':11' = 'go'
-- Equation name is 'go', location is LC7_C6, type is buried.
go = DFFE( VCC, GLOBAL(!qd), !_LC5_C6, VCC, VCC);
-- Node name is ':17' = 'qq0'
-- Equation name is 'qq0', location is LC1_C6, type is buried.
!qq0 = qq0~NOT;
qq0~NOT = DFFE( _EQ001, GLOBAL( clk), !_LC2_C8, VCC, VCC);
_EQ001 = go & !qd & qq0
# !go & !qq0
# qd & !qq0;
-- Node name is ':16' = 'qq1'
-- Equation name is 'qq1', location is LC2_C6, type is buried.
!qq1 = qq1~NOT;
qq1~NOT = DFFE( _EQ002, GLOBAL( clk), !_LC2_C8, VCC, VCC);
_EQ002 = !qq0 & !qq1
# !go & !qq1
# qd & !qq1
# go & !qd & qq0 & qq1;
-- Node name is ':15' = 'qq2'
-- Equation name is 'qq2', location is LC3_C6, type is buried.
!qq2 = qq2~NOT;
qq2~NOT = DFFE( _EQ003, GLOBAL( clk), !_LC2_C8, VCC, VCC);
_EQ003 = !qq0 & !qq2
# !qq1 & !qq2
# !_LC8_C6 & !qq2
# _LC8_C6 & qq0 & qq1 & qq2;
-- Node name is 't1'
-- Equation name is 't1', type is output
t1 = _LC6_C8;
-- Node name is 't2'
-- Equation name is 't2', type is output
t2 = _LC3_C8;
-- Node name is 't3'
-- Equation name is 't3', type is output
t3 = _LC5_C8;
-- Node name is 't4'
-- Equation name is 't4', type is output
t4 = _LC1_C8;
-- Node name is ':104'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = LCELL( _EQ004);
_EQ004 = go & !qd;
-- Node name is ':160'
-- Equation name is '_LC4_C6', type is buried
!_LC4_C6 = _LC4_C6~NOT;
_LC4_C6~NOT = LCELL( _EQ005);
_EQ005 = !qq2
# qq0
# qq1;
-- Node name is ':164'
-- Equation name is '_LC2_C8', type is buried
!_LC2_C8 = _LC2_C8~NOT;
_LC2_C8~NOT = LCELL( _EQ006);
_EQ006 = !qq2 & !tj
# qq0 & !tj
# qq1 & !tj;
-- Node name is ':190'
-- Equation name is '_LC5_C6', type is buried
!_LC5_C6 = _LC5_C6~NOT;
_LC5_C6~NOT = LCELL( _EQ007);
_EQ007 = !dan & !dp & !qd
# !_LC4_C6;
-- Node name is ':302'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ008);
_EQ008 = !qq0 & !qq1 & !qq2 & !tj;
-- Node name is ':307'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ009);
_EQ009 = qq0 & !qq1 & !qq2 & !tj;
-- Node name is ':312'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ010);
_EQ010 = !qq0 & qq1 & !qq2 & !tj;
-- Node name is ':317'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ011);
_EQ011 = qq0 & qq1 & !qq2 & !tj;
Project Information c:\maxplus2\multi\cpu\shixu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,541K
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